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ARM926ejs MMU problem

Prasanna Barve
Note: This was originally posted on 17th December 2010 at http://forums.arm.com

I am working on an ARM926ejs core (Fiujitsu) with Linux as the OS.

I am trying to disable the MMU and re enable it again. I read lot of articles on the net and tried to follow the same procedure:
1. Invalidate D-cache (and I-cache)
2. Invalidated TLB
3. Disable MMU

however, I observed that as soon as I turned OFF the MMU the system got stuck, but if I run the same code without disabling the MMU, it works fine.
I want to know what exactly is going wrong after the MMU is disabled?

Following is the code snipped I used to disable the MMU:
     /* The Instruction and Data Cache are disabled:: code not pasted here */   

     mov   r0,#0
    
     /* Invalidate TLB */
     mcr  p15, 0, r0, c8, c7, 0

#if 1
     nop
     mcr  p15, 0, r2, c1, c0, 0   /* Disable MMU */
     mov  r2,r2                /* these could be in pipeline with MVA */
     mov  r2,r2                /* these could be in pipeline with MVA */
     mov  r2,r2                /* these could be in pipeline with MVA */
     mov  pc,r10               /* jump to Enable MMU: this could be the actual PA to jump */
#endif


I tried to disable the "Instruction Prefetch" in the co-processor c15 register. I've been struggling to get this to work for the past one month and unable to get the desired outcome.
If there's anyone who could help me solve this, I would greatly appreciate.
  • Note: This was originally posted on 21st December 2010 at http://forums.arm.com

    Thanks guys for your inputs.

    How do I ensure that the instruction at the VA is the same as that of f(VA)?
    Due to the pipelining, the instructions are prefetched by the core, so when the MMU is enabled, there still are some instructions in the pipeline (decoded from VA, i guess)?

    Actually, I am not using any C libraries, and I am disabling the IRQ and FIQ before jumping into the Assembly code, so I guess it wont be a problem either?

    I am not much conversant with the Page Table entries yet, especially on the Linux platform. Can you please elaborate a little more on this?
    As I know, when the linux kerel boots, it creates the Page Table (in the RAM) before enabling the MMU; the PTEs contain the mapping of the Physical RAM space into the Virtual space? I do not have full understanding yet, so I may be wrong.

    The reason I am trying to disable and reenable the MMU is for implementing Power management : by disabling, I will copy the power management code into the internal SRAM OR the ITCM of the SoC, reenable the MMU and continue. Once the power down event is detected by application, again the MMU will have to be turned OFF before jumping into the SRAM/ITCM to execute the Wait-For_Interrupt (WFI) instruction (other booking, if  any, will also be done before this). Is this approach correct?



    As soon as you disable the MMU, the address translation will become flat mapped.

    Before you turn the MMU off, the instructions at VA are being fetched from PA = f(VA), after you turn it off, the instructions at VA are fetched from PA = VA.

    Have you ensured that the instructions at VA are the same as f(VA), or have you ensured that the page you are executing from before you disable the MMU is already flat mapped?

    Further, if something subsequently makes use of the stack (or C library) have you ensured these have valid mappings with the MMU disabled?

    hth
    s.
  • Arm Employee Badge
    Note: This was originally posted on 17th December 2010 at http://forums.arm.com

    You do not have to invalidate the TLB before disabling the MMU, but you may need to do so before re-enabling.  On the cache side, you need to clean the data cache before the MMU is disabled, and invalidate the caches before re-enabling the MMU,

    I have a dim memory that to disable the MMU the code that does so must be flat mapped (VA==PA).
  • Arm Employee Badge
    Note: This was originally posted on 17th December 2010 at http://forums.arm.com

    As soon as you disable the MMU, the address translation will become flat mapped.

    Before you turn the MMU off, the instructions at VA are being fetched from PA = f(VA), after you turn it off, the instructions at VA are fetched from PA = VA.

    Have you ensured that the instructions at VA are the same as f(VA), or have you ensured that the page you are executing from before you disable the MMU is already flat mapped?

    Further, if something subsequently makes use of the stack (or C library) have you ensured these have valid mappings with the MMU disabled?

    hth
    s.