Arm Development Studio forum Dual Issue and Pipeline stalls

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Dual Issue and Pipeline stalls

Note: This was originally posted on 27th August 2010 at http://forums.arm.com

Hi,

I have the following situation in my current work. Please explain in case of any pipeline stall or preventing dual issue chance.

    LDRB     R2,[R0,#2]
    LDRB     R1,[R0,#1]
VLD1.32 {D4,D5},[R7]
    VLD1.32 {D22,D23},[R8]
VADD.I32 Q2,Q2,Q11
STR      R2,[R5]
    STR      R1,[R5]

In another instant the following situation comes

        VADD.I32 Q2,Q11,Q2
    VADD.I32 Q2,Q2,Q9
    VSHR.S32 Q11,Q2,#1
    VCGT.S32 Q2,Q11,Q0
    VLD1.32 {D22,D23},[R4]
    VBSL     Q2,Q12,Q13
    VADD.I32 Q2,Q11,Q2
    VADD.I32 Q2,Q2,Q10
    VST1.32 {D4,D5},[R1]

In this set of instruction any chance for any types of pipeline stalls in a Cortex A8 processor.

Thanks
Dave.