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Cacheable setting in TTBR and Page descriptors

KyongHo Cho
Note: This was originally posted on 24th February 2010 at http://forums.arm.com

Hi there!

While reading the ARMv7-AR reference manual,
we have to configure cacheable settings on both of TTB registers and page descriptors.

The followings list same settings in TTBR and page descriptors:
S : shareable
RGN / TEX,C,B : inner and outer cacheable

As I know, TEX, C, B and S bits in the page descriptors are applied to the page described by the page descriptor.

I guess the meaning of S and RGN bits in TTBR as below:
1. those bits are not the settings for pages related to the TTBR but for page tables themselves.
   But I don't think this is correct because there is already a cache for page tables, TLB.
2. those bits are the settings for the whole address space of a task whose page table is
   referenced by the current TTBR. Cacheability and shareability settings in the page descriptors
   override that settings in TTBR.

Thank you in advance!;
Parents
  • Note: This was originally posted on 3rd December 2010 at http://forums.arm.com


    The RGN bits in the TTB registers are only used for table walks by the MMU,

    For it to work reliably - the options chosen with the RGN bits must match what is used when accessing the same memory normally (e.g. due to modifying the page tables)


    Hi,
    could you provide me example settings? I tried on a Cortex-A8 (BeagleBoard) with the following settings, but still have to flush the data cache to get level 2 table changes effective. Level 1 table changes, however, become effective without the need to flush the data cache.

    Page tables on cached memory (TEX=0, S=0, C=1, B=1)
    TTB registers have RGN=11, C=1, S=0
    Caches and BTB are enabled

    Thanks a lot,
    Robert
Reply
  • Note: This was originally posted on 3rd December 2010 at http://forums.arm.com


    The RGN bits in the TTB registers are only used for table walks by the MMU,

    For it to work reliably - the options chosen with the RGN bits must match what is used when accessing the same memory normally (e.g. due to modifying the page tables)


    Hi,
    could you provide me example settings? I tried on a Cortex-A8 (BeagleBoard) with the following settings, but still have to flush the data cache to get level 2 table changes effective. Level 1 table changes, however, become effective without the need to flush the data cache.

    Page tables on cached memory (TEX=0, S=0, C=1, B=1)
    TTB registers have RGN=11, C=1, S=0
    Caches and BTB are enabled

    Thanks a lot,
    Robert
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