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Cacheable setting in TTBR and Page descriptors
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Cacheable setting in TTBR and Page descriptors
KyongHo Cho
over 12 years ago
Note: This was originally posted on 24th February 2010 at
http://forums.arm.com
Hi there!
While reading the ARMv7-AR reference manual,
we have to configure cacheable settings on both of TTB registers and page descriptors.
The followings list same settings in TTBR and page descriptors:
S : shareable
RGN / TEX,C,B : inner and outer cacheable
As I know, TEX, C, B and S bits in the page descriptors are applied to the page described by the page descriptor.
I guess the meaning of S and RGN bits in TTBR as below:
1. those bits are not the settings for pages related to the TTBR but for page tables themselves.
But I don't think this is correct because there is already a cache for page tables, TLB.
2. those bits are the settings for the whole address space of a task whose page table is
referenced by the current TTBR. Cacheability and shareability settings in the page descriptors
override that settings in TTBR.
Thank you in advance!;
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