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Cacheable setting in TTBR and Page descriptors

KyongHo Cho
Note: This was originally posted on 24th February 2010 at http://forums.arm.com

Hi there!

While reading the ARMv7-AR reference manual,
we have to configure cacheable settings on both of TTB registers and page descriptors.

The followings list same settings in TTBR and page descriptors:
S : shareable
RGN / TEX,C,B : inner and outer cacheable

As I know, TEX, C, B and S bits in the page descriptors are applied to the page described by the page descriptor.

I guess the meaning of S and RGN bits in TTBR as below:
1. those bits are not the settings for pages related to the TTBR but for page tables themselves.
   But I don't think this is correct because there is already a cache for page tables, TLB.
2. those bits are the settings for the whole address space of a task whose page table is
   referenced by the current TTBR. Cacheability and shareability settings in the page descriptors
   override that settings in TTBR.

Thank you in advance!;
Parents
  • Note: This was originally posted on 25th February 2010 at http://forums.arm.com

    Thank you for your reply!

    According to your answer, D-cache is used when MMU does translation table walk and when O/S manages page tables.
    Are the RGN and S fields in TTBR applied to the both cases?

    When looking into the source code of Linux,
    O/S just writes a page descriptor to a virtual memory address as a ordinary data.
    I thought that means RGN is not applied to this case.

    If D-cache is also used by MMU while translation table walk,
    are multiple page descriptors cached in D-cache and a page descriptor is cached in TLB whenever it is required?
Reply
  • Note: This was originally posted on 25th February 2010 at http://forums.arm.com

    Thank you for your reply!

    According to your answer, D-cache is used when MMU does translation table walk and when O/S manages page tables.
    Are the RGN and S fields in TTBR applied to the both cases?

    When looking into the source code of Linux,
    O/S just writes a page descriptor to a virtual memory address as a ordinary data.
    I thought that means RGN is not applied to this case.

    If D-cache is also used by MMU while translation table walk,
    are multiple page descriptors cached in D-cache and a page descriptor is cached in TLB whenever it is required?
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