This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cacheable setting in TTBR and Page descriptors

Note: This was originally posted on 24th February 2010 at http://forums.arm.com

Hi there!

While reading the ARMv7-AR reference manual,
we have to configure cacheable settings on both of TTB registers and page descriptors.

The followings list same settings in TTBR and page descriptors:
S : shareable
RGN / TEX,C,B : inner and outer cacheable

As I know, TEX, C, B and S bits in the page descriptors are applied to the page described by the page descriptor.

I guess the meaning of S and RGN bits in TTBR as below:
1. those bits are not the settings for pages related to the TTBR but for page tables themselves.
   But I don't think this is correct because there is already a cache for page tables, TLB.
2. those bits are the settings for the whole address space of a task whose page table is
   referenced by the current TTBR. Cacheability and shareability settings in the page descriptors
   override that settings in TTBR.

Thank you in advance!;

Parents

Martin Weidmann over 12 years ago

Note: This was originally posted on 26th February 2010 at http://forums.arm.com

The RGN bits in the TTB registers are only used for table walks by the MMU,

For it to work reliably - the options chosen with the RGN bits must match what is used when accessing the same memory normally (e.g. due to modifying the page tables)
Cancel
Vote up 0 Vote down

Cancel

Reply

Martin Weidmann over 12 years ago

Note: This was originally posted on 26th February 2010 at http://forums.arm.com

The RGN bits in the TTB registers are only used for table walks by the MMU,

For it to work reliably - the options chosen with the RGN bits must match what is used when accessing the same memory normally (e.g. due to modifying the page tables)
Cancel
Vote up 0 Vote down

Cancel

Children

No data