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Load/Store instruction cycle calculation

Chintan Dave
Note: This was originally posted on 23rd February 2010 at http://forums.arm.com

Hi,
    LDR instruction in cortex-m3 require 2 pipeline cycle means 6 clock cycle. 2-cycle is require for fetch and decode. In 3rd cycle address calculated and send to memory. Memory will sample the address in 4th clock cycle and put data on bus.In 5th clock cycle master will sample the input data and load register on negative edge of clock .Where the 6th clock cycle is utilise? (Here i am loading my register on negative edge of clock)
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  • Arm Employee Badge
    Note: This was originally posted on 4th March 2010 at http://forums.arm.com

    Cortex-M3 is an AHB-Lite master; AHB operates on the positive edge of the clock only, so the master will not sample data on the negative clock edge.

    I'm not really sure what your question is; the Cortex-M3 TRM indicates that single load/stores consume either one or two execute/issue cycles depending on what other instructions they are paired with. Additional cycles will be required to fetch and decode these instructions, but these will be hidden by the execution of other instructions.

    Cortex-M3's memory interface is AHB-Lite; this means the address must be sampled on a rising edge of HCLK when HREADY is high, and the read data must be provided for the following rising edge of HCLK on which HREADY is high (delays/waitstates may be inserted by driving HREADY low for any number of HCLK cycles).

    I'm not sure where your use of negative-clock-edges or six clock cycles come from.

    hth
    s.
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  • Arm Employee Badge
    Note: This was originally posted on 4th March 2010 at http://forums.arm.com

    Cortex-M3 is an AHB-Lite master; AHB operates on the positive edge of the clock only, so the master will not sample data on the negative clock edge.

    I'm not really sure what your question is; the Cortex-M3 TRM indicates that single load/stores consume either one or two execute/issue cycles depending on what other instructions they are paired with. Additional cycles will be required to fetch and decode these instructions, but these will be hidden by the execution of other instructions.

    Cortex-M3's memory interface is AHB-Lite; this means the address must be sampled on a rising edge of HCLK when HREADY is high, and the read data must be provided for the following rising edge of HCLK on which HREADY is high (delays/waitstates may be inserted by driving HREADY low for any number of HCLK cycles).

    I'm not sure where your use of negative-clock-edges or six clock cycles come from.

    hth
    s.
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