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Load/Store instruction cycle calculation

Chintan Dave
Note: This was originally posted on 23rd February 2010 at http://forums.arm.com

Hi,
    LDR instruction in cortex-m3 require 2 pipeline cycle means 6 clock cycle. 2-cycle is require for fetch and decode. In 3rd cycle address calculated and send to memory. Memory will sample the address in 4th clock cycle and put data on bus.In 5th clock cycle master will sample the input data and load register on negative edge of clock .Where the 6th clock cycle is utilise? (Here i am loading my register on negative edge of clock)
  • Note: This was originally posted on 10th March 2010 at http://forums.arm.com

    Cortex-M3 is an AHB-Lite master; AHB operates on the positive edge of the clock only, so the master will not sample data on the negative clock edge.

    I'm not really sure what your question is; the Cortex-M3 TRM indicates that single load/stores consume either one or two execute/issue cycles depending on what other instructions they are paired with. Additional cycles will be required to fetch and decode these instructions, but these will be hidden by the execution of other instructions.

    Cortex-M3's memory interface is AHB-Lite; this means the address must be sampled on a rising edge of HCLK when HREADY is high, and the read data must be provided for the following rising edge of HCLK on which HREADY is high (delays/waitstates may be inserted by driving HREADY low for any number of HCLK cycles).

    I'm not sure where your use of negative-clock-edges or six clock cycles come from.

    hth
    s.


    Hi,
      Thanks for reply. In Cortex M3, most of the instruction(for example AND instruction) executed by alu unit require 3-clock cycle.2-cycle for fetch and decode. In 3rd posedge clock alu execution unit will sample the data coming from decoder and calculate the result which it has to update in destination register in the same cycle because its 3-clock cycle operation. So i must utilise the negative edge of clock to update the destination register value. That means my Register file Unit which is updating register value is working at negative edge of clock.

    In TRM its written that LDR require 2 pipeline cycle or we can say 6 clock cycle because its 3-stage pipeline. 2-clock cycle is require for fetch and decode. In 3rd posedge of clock cycle load/store unit will calculate address and send to memory. Memory will sample the address in 4th posedge clock cycle and put data on bus.In 5th posedge clock cycle master will sample the data send by memory. Now here is the problem. Register is updating in negative edge of 5th clock. Operation is complete in 5-cycle. What is the utilization of 6th clock cycle.

    If u know,Can u explain me the operation of LDR instruction with respect to 6 clock cycle?

    Now problem come for LDR.
  • Note: This was originally posted on 12th March 2010 at http://forums.arm.com

    You appear to be confusing "pipeline stages" and "cycles", and appear to be making assumptions about the number of clock-cycles per machine-cycle Cortex-M3 implements; dare I ask what you are trying to do?

    s.


    Hi,
       I just want to know how many cycle is require to execute LDR instruction. In TRM its written 2-pipeline cycle. If i am not wrong,single pipeline cycle is same as 3-clock cycle if we consider fetch,decode and execute stage. If i am wrong, can u tell me the meaning of 2-pipeline cycle and how LDR instruction is executed with respect to clock cycle.
  • Note: This was originally posted on 18th March 2010 at http://forums.arm.com

    A single pipeline cycle is the same as a single clock cycle;
    thus a two cycle load appears to consume two clock cycles.
    It might be worth looking at [url="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337g/BABCJEHC.html"]infocenter.arm.com/.../url]

    hth
    s.


    Hi,
        Can u explain me what is happening in two cycle when LDR instruction is executing?
  • Note: This was originally posted on 19th March 2010 at http://forums.arm.com

    AHB requires one cycle for address and another cycle for data.

    hth
    s.


    Thats right but when load/store unit puts address on to bus, slave will not have address on the same clock edge because of some delay on bus. It sample the address in 2nd clock cycle and put apporopriate data on the same cycle and master will sample the data in 3rd clock cycle.  If you see the waveform with respect to clock in AHB AMBA specification  same case is there. Here you have not cosider the delay of bus. Why is it so? (Consider this is first instruction in load/store execution unit or no previous load/store instruction is executing before it)
  • Arm Employee Badge
    Note: This was originally posted on 10th March 2010 at http://forums.arm.com

    You appear to be confusing "pipeline stages" and "cycles", and appear to be making assumptions about the number of clock-cycles per machine-cycle Cortex-M3 implements; dare I ask what you are trying to do?

    s.
  • Arm Employee Badge
    Note: This was originally posted on 4th March 2010 at http://forums.arm.com

    Cortex-M3 is an AHB-Lite master; AHB operates on the positive edge of the clock only, so the master will not sample data on the negative clock edge.

    I'm not really sure what your question is; the Cortex-M3 TRM indicates that single load/stores consume either one or two execute/issue cycles depending on what other instructions they are paired with. Additional cycles will be required to fetch and decode these instructions, but these will be hidden by the execution of other instructions.

    Cortex-M3's memory interface is AHB-Lite; this means the address must be sampled on a rising edge of HCLK when HREADY is high, and the read data must be provided for the following rising edge of HCLK on which HREADY is high (delays/waitstates may be inserted by driving HREADY low for any number of HCLK cycles).

    I'm not sure where your use of negative-clock-edges or six clock cycles come from.

    hth
    s.
  • Arm Employee Badge
    Note: This was originally posted on 12th March 2010 at http://forums.arm.com

    A single pipeline cycle is the same as a single clock cycle;
    thus a two cycle load appears to consume two clock cycles.
    It might be worth looking at [url="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337g/BABCJEHC.html"]http://infocenter.arm.com/help/topic/com.a...g/BABCJEHC.html[/url]

    hth
    s.
  • Arm Employee Badge
    Note: This was originally posted on 19th March 2010 at http://forums.arm.com

    Can u explain me what is happening in two cycle when LDR instruction is executing


    AHB requires one cycle for address and another cycle for data.

    hth
    s.