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Load/Store instruction cycle calculation

Note: This was originally posted on 23rd February 2010 at http://forums.arm.com

Hi,
LDR instruction in cortex-m3 require 2 pipeline cycle means 6 clock cycle. 2-cycle is require for fetch and decode. In 3rd cycle address calculated and send to memory. Memory will sample the address in 4th clock cycle and put data on bus.In 5th clock cycle master will sample the input data and load register on negative edge of clock .Where the 6th clock cycle is utilise? (Here i am loading my register on negative edge of clock)

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Simon Craske over 12 years ago

Note: This was originally posted on 10th March 2010 at http://forums.arm.com

You appear to be confusing "pipeline stages" and "cycles", and appear to be making assumptions about the number of clock-cycles per machine-cycle Cortex-M3 implements; dare I ask what you are trying to do?

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Simon Craske over 12 years ago

Note: This was originally posted on 10th March 2010 at http://forums.arm.com

You appear to be confusing "pipeline stages" and "cycles", and appear to be making assumptions about the number of clock-cycles per machine-cycle Cortex-M3 implements; dare I ask what you are trying to do?

s.
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