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Load/Store instruction cycle calculation

Chintan Dave
Note: This was originally posted on 23rd February 2010 at http://forums.arm.com

Hi,
    LDR instruction in cortex-m3 require 2 pipeline cycle means 6 clock cycle. 2-cycle is require for fetch and decode. In 3rd cycle address calculated and send to memory. Memory will sample the address in 4th clock cycle and put data on bus.In 5th clock cycle master will sample the input data and load register on negative edge of clock .Where the 6th clock cycle is utilise? (Here i am loading my register on negative edge of clock)
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  • Note: This was originally posted on 19th March 2010 at http://forums.arm.com

    AHB requires one cycle for address and another cycle for data.

    hth
    s.


    Thats right but when load/store unit puts address on to bus, slave will not have address on the same clock edge because of some delay on bus. It sample the address in 2nd clock cycle and put apporopriate data on the same cycle and master will sample the data in 3rd clock cycle.  If you see the waveform with respect to clock in AHB AMBA specification  same case is there. Here you have not cosider the delay of bus. Why is it so? (Consider this is first instruction in load/store execution unit or no previous load/store instruction is executing before it)
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  • Note: This was originally posted on 19th March 2010 at http://forums.arm.com

    AHB requires one cycle for address and another cycle for data.

    hth
    s.


    Thats right but when load/store unit puts address on to bus, slave will not have address on the same clock edge because of some delay on bus. It sample the address in 2nd clock cycle and put apporopriate data on the same cycle and master will sample the data in 3rd clock cycle.  If you see the waveform with respect to clock in AHB AMBA specification  same case is there. Here you have not cosider the delay of bus. Why is it so? (Consider this is first instruction in load/store execution unit or no previous load/store instruction is executing before it)
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