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Load/Store instruction cycle calculation

Chintan Dave
Note: This was originally posted on 23rd February 2010 at http://forums.arm.com

Hi,
    LDR instruction in cortex-m3 require 2 pipeline cycle means 6 clock cycle. 2-cycle is require for fetch and decode. In 3rd cycle address calculated and send to memory. Memory will sample the address in 4th clock cycle and put data on bus.In 5th clock cycle master will sample the input data and load register on negative edge of clock .Where the 6th clock cycle is utilise? (Here i am loading my register on negative edge of clock)
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  • Note: This was originally posted on 12th March 2010 at http://forums.arm.com

    You appear to be confusing "pipeline stages" and "cycles", and appear to be making assumptions about the number of clock-cycles per machine-cycle Cortex-M3 implements; dare I ask what you are trying to do?

    s.


    Hi,
       I just want to know how many cycle is require to execute LDR instruction. In TRM its written 2-pipeline cycle. If i am not wrong,single pipeline cycle is same as 3-clock cycle if we consider fetch,decode and execute stage. If i am wrong, can u tell me the meaning of 2-pipeline cycle and how LDR instruction is executed with respect to clock cycle.
Reply
  • Note: This was originally posted on 12th March 2010 at http://forums.arm.com

    You appear to be confusing "pipeline stages" and "cycles", and appear to be making assumptions about the number of clock-cycles per machine-cycle Cortex-M3 implements; dare I ask what you are trying to do?

    s.


    Hi,
       I just want to know how many cycle is require to execute LDR instruction. In TRM its written 2-pipeline cycle. If i am not wrong,single pipeline cycle is same as 3-clock cycle if we consider fetch,decode and execute stage. If i am wrong, can u tell me the meaning of 2-pipeline cycle and how LDR instruction is executed with respect to clock cycle.
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