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Cortex-M3 is an AHB-Lite master; AHB operates on the positive edge of the clock only, so the master will not sample data on the negative clock edge.I'm not really sure what your question is; the Cortex-M3 TRM indicates that single load/stores consume either one or two execute/issue cycles depending on what other instructions they are paired with. Additional cycles will be required to fetch and decode these instructions, but these will be hidden by the execution of other instructions.Cortex-M3's memory interface is AHB-Lite; this means the address must be sampled on a rising edge of HCLK when HREADY is high, and the read data must be provided for the following rising edge of HCLK on which HREADY is high (delays/waitstates may be inserted by driving HREADY low for any number of HCLK cycles).I'm not sure where your use of negative-clock-edges or six clock cycles come from.hths.