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memory barrier

mosfet mosfet
Note: This was originally posted on 18th January 2010 at http://forums.arm.com

Hi,

On x86/win architecture there is a function called MemoryBarrier that prevents the CPU from re-ordering read/write operations.
Is there something like that on arm architecture ?

// x86

FORCEINLINE VOID
MemoryBarrier (VOID)
{
    LONG Barrier;
    __asm {
        xchg Barrier, eax
    }
}
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  • Note: This was originally posted on 20th January 2010 at http://forums.arm.com

    On some ARM processors there are multiple bus interfaces, for example, ARM1136 have separated read and write data bus. From my understanding, SWP and SWPB can only ensure the read and write transfers are atomic, but it does not imply a barrier behavior ( it might be true in some ARM processors but it is not a necessary requirement). 
    In newer ARM processors semaphores operations can be handled by exclusive accesses (LDREX, STREX, etc).  These instructions can work together with barrier instructions to ensure safe memory ordering in semaphores.
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  • Note: This was originally posted on 20th January 2010 at http://forums.arm.com

    On some ARM processors there are multiple bus interfaces, for example, ARM1136 have separated read and write data bus. From my understanding, SWP and SWPB can only ensure the read and write transfers are atomic, but it does not imply a barrier behavior ( it might be true in some ARM processors but it is not a necessary requirement). 
    In newer ARM processors semaphores operations can be handled by exclusive accesses (LDREX, STREX, etc).  These instructions can work together with barrier instructions to ensure safe memory ordering in semaphores.
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