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memory barrier

Note: This was originally posted on 18th January 2010 at http://forums.arm.com

Hi,

On x86/win architecture there is a function called MemoryBarrier that prevents the CPU from re-ordering read/write operations.
Is there something like that on arm architecture ?

// x86

FORCEINLINE VOID
MemoryBarrier (VOID)
{
    LONG Barrier;
    __asm {
        xchg Barrier, eax
    }
}

zart zurt over 12 years ago

Note: This was originally posted on 19th January 2010 at http://forums.arm.com

Hi,

On x86/win architecture there is a function called MemoryBarrier that prevents the CPU from re-ordering read/write operations.
Is there something like that on arm architecture ?

// x86

FORCEINLINE VOID
MemoryBarrier (VOID)
{
    LONG Barrier;
    __asm {
        xchg Barrier, eax
    }
}

Maybe this helps
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.kui0098a/armccref_cjaefhhi.htm

You may also have to issue this depending on the situation
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.kui0098a/armccref_cjafigeg.htm
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zart zurt over 12 years ago

Note: This was originally posted on 20th January 2010 at http://forums.arm.com

Older generations of ARM processors (e.g. ARM7TDMI) does not have memory barrier instructions.
Newer ARM processors (all Cortex-A, Cortex-R and Cortex-M processors) have memory barrier instructions

Thanks for the info...

By looking at the example of x86
Do you think SWP or SWPB does
the same thing XCHG does on x86 ?

As SWP blocks the SystemBus, I think
the core should write any outstanding write
ops before executing this instruction, any thought ?
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guestposter guestposter over 12 years ago

Note: This was originally posted on 19th January 2010 at http://forums.arm.com

Older generations of ARM processors (e.g. ARM7TDMI) does not have memory barrier instructions.
Newer ARM processors (all Cortex-A, Cortex-R and Cortex-M processors) have memory barrier instructions:
http://www.keil.com/support/man/docs/armasm/
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guestposter guestposter over 12 years ago

Note: This was originally posted on 20th January 2010 at http://forums.arm.com

On some ARM processors there are multiple bus interfaces, for example, ARM1136 have separated read and write data bus. From my understanding, SWP and SWPB can only ensure the read and write transfers are atomic, but it does not imply a barrier behavior ( it might be true in some ARM processors but it is not a necessary requirement).
In newer ARM processors semaphores operations can be handled by exclusive accesses (LDREX, STREX, etc). These instructions can work together with barrier instructions to ensure safe memory ordering in semaphores.
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