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memory barrier

mosfet mosfet
Note: This was originally posted on 18th January 2010 at http://forums.arm.com

Hi,

On x86/win architecture there is a function called MemoryBarrier that prevents the CPU from re-ordering read/write operations.
Is there something like that on arm architecture ?

// x86

FORCEINLINE VOID
MemoryBarrier (VOID)
{
    LONG Barrier;
    __asm {
        xchg Barrier, eax
    }
}
Parents
  • Note: This was originally posted on 20th January 2010 at http://forums.arm.com

    Older generations of ARM processors (e.g. ARM7TDMI) does not have memory barrier instructions.
    Newer ARM processors (all Cortex-A, Cortex-R and Cortex-M processors) have memory barrier instructions


    Thanks for the info...

    By looking at the example of x86
    Do you think SWP or SWPB does
    the same thing XCHG does on x86 ?

    As SWP blocks the SystemBus, I think
    the core should write any outstanding write
    ops before executing this instruction, any thought ?
Reply
  • Note: This was originally posted on 20th January 2010 at http://forums.arm.com

    Older generations of ARM processors (e.g. ARM7TDMI) does not have memory barrier instructions.
    Newer ARM processors (all Cortex-A, Cortex-R and Cortex-M processors) have memory barrier instructions


    Thanks for the info...

    By looking at the example of x86
    Do you think SWP or SWPB does
    the same thing XCHG does on x86 ?

    As SWP blocks the SystemBus, I think
    the core should write any outstanding write
    ops before executing this instruction, any thought ?
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