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CPU1 state after boot monitor?

Note: This was originally posted on 13th October 2009 at http://forums.arm.com

Hello Experts,

There are two Cores in ARM PBX-A9 develop board: cpu0 and cpu1. Does anyone know the state of cpu1 while boot monitor is running.

Below are the boot info:

ARM PBX Boot Monitor
Version: V4.1.7
Build Date: Feb 17 2009
Tile Site 1: Cortex A9 with 2 cores
Tile Site 2: Tile Not Fitted
Endian: Little

I just suspect that if cpu1 is waiting the non-zero value for SYS_FLAGS(address is 0x10000030) register and then jump into that value. However, if I wrote a valid routines address in SYS_FLAGS register, it's not performed by cpu1.

Thanks much for any of your response!

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Zhanguo Li over 12 years ago

Note: This was originally posted on 14th October 2009 at http://forums.arm.com

It turned out that the CPU1's "Pending clear registers" need be cleared if CPU0 want to send a software interrupt to wake up CPU1. But my questions about "Processor Interface Implementer Identification Register" still exist.
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Zhanguo Li over 12 years ago

Note: This was originally posted on 14th October 2009 at http://forums.arm.com

It turned out that the CPU1's "Pending clear registers" need be cleared if CPU0 want to send a software interrupt to wake up CPU1. But my questions about "Processor Interface Implementer Identification Register" still exist.
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