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Cache hit and miss

Note: This was originally posted on 16th September 2009 at http://forums.arm.com

Hi
I am using RVDS 4.0 I am running my code ARM926EJ-S RVISS core simulator.
Can anyone tell me is it possible to detect cache hit/ miss in simulator ? If so how to find cache hit/miss in simulator?
Regards,
Manish
  • Note: This was originally posted on 17th September 2009 at http://forums.arm.com

    You need to edit the default.ami configuration file for RVISS ($ARMROOT\RVARMulator\ARMulator\1.4.1\313\win_32-pentium).  Find the this line:

    Counters=false

    Change it to true.  Next time you connect to RVISS in RVD, find the CycleCount tab in the register pane.



    I get the cycle count tab but I could not locate any field which corresponds to cache hit/miss. The fields corresponds to various cycles like instructions, core cycles, idle cycles, busy cycles, seq and no-seq cycles but nothing related to cache hit/ miss.
    In RVDS I get Cache operation tab and Cache lockdown tab but the entries in these tabs are inactive (grayed out while running my program. While selecting the target for connection in RVDS I select default Page-Tables for MMU/ MPU initialization. When this option is selected the cycles taken to exceute my code are 40 % less than when the option is not selected.  But in bothe cases cache related tabs are inactive.
    So can you tell me weather cache hit/miss can be detected in RVDS simulator? Or do I need hardware for detecting cache hit/ miss counts.
  • Note: This was originally posted on 17th September 2009 at http://forums.arm.com

    You need to edit the default.ami configuration file for RVISS ($ARMROOT\RVARMulator\ARMulator\1.4.1\313\win_32-pentium).  Find the this line:

    Counters=false

    Change it to true.  Next time you connect to RVISS in RVD, find the CycleCount tab in the register pane.
  • Note: This was originally posted on 17th September 2009 at http://forums.arm.com

    Strange, after the config file edit I see more stats.  See attachment...