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does the BUFFERABLE bit of HPROT/AxCACHE ever mean anything by itself?

Note: This was originally posted on 31st July 2009 at http://forums.arm.com

hi all,

there seems to be a clear definition of "bufferable" in both the AHB and AXI specs, pertaining to where write responses must be issued from. but, then there are tables like the following from an ARM10 manual, which makes it seems like bufferable doesn't mean anything by itself:

C B Notes
0 0 Uncached, unbuffered
0 1 Uncached, buffered
1 0 Write-through cached, buffered
1 1 Write-back cached, buffered[/font]

for both AHB and AXI, does the bufferable bit always have to be interpreted along with the cacheable bit?

another thread seems to imply this:
[url="http://forums.arm.com/index.php?showtopic=12871"]http://forums.arm.com/index.php?showtopic=12871[/url]

any other official statements to this effect?

thanks!
james

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Martin Weidmann over 12 years ago

Note: This was originally posted on 31st July 2009 at http://forums.arm.com

The answer is slightly different for AXI and AHB. I suggest you get copies of both of the specifications, you can request them through ARM's website.
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Martin Weidmann over 12 years ago

Note: This was originally posted on 31st July 2009 at http://forums.arm.com

The answer is slightly different for AXI and AHB. I suggest you get copies of both of the specifications, you can request them through ARM's website.
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