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does the BUFFERABLE bit of HPROT/AxCACHE ever mean anything by itself?

jameskim jameskim
Note: This was originally posted on 31st July 2009 at http://forums.arm.com

hi all,

there seems to be a clear definition of "bufferable" in both the AHB and AXI specs, pertaining to where write responses must be issued from.  but, then there are tables like the following from an ARM10 manual, which makes it seems like bufferable doesn't mean anything by itself:

C  B  Notes
0  0  Uncached, unbuffered
0  1  Uncached, buffered
1  0  Write-through cached, buffered
1  1  Write-back cached, buffered[/font]

for both AHB and AXI, does the bufferable bit always have to be interpreted along with the cacheable bit?

another thread seems to imply this:
[url="http://forums.arm.com/index.php?showtopic=12871"]http://forums.arm.com/index.php?showtopic=12871[/url]

any other official statements to this effect?

thanks!
james
  • Note: This was originally posted on 27th October 2009 at http://forums.arm.com

    The answer is slightly different for AXI and AHB.  I suggest you get copies of both of the specifications, you can request them through ARM's website.


    thanks.  i have both copies of the specs and it seems to me that for cacheable requests, the bufferable bit distinguishes between write-through and write-back.  but, non-cacheable requests there are bufferable and non-bufferable accesses.  assuming that write-through requests are bufferable, it seems that the bufferable bit has to be interpreted after looking at the cacheable bit.  does that sound right?
  • Arm Employee Badge
    Note: This was originally posted on 31st July 2009 at http://forums.arm.com

    The answer is slightly different for AXI and AHB.  I suggest you get copies of both of the specifications, you can request them through ARM's website.
  • Arm Employee Badge
    Note: This was originally posted on 28th October 2009 at http://forums.arm.com

    Yes, that sounds right to me. The pair of bits describe the memory type you are accessing, and therefore what the bus / cache infrastructure is allowed to do with it. Interpreting either of these bits individually only gives a partial picture of the memory type, and is pretty meaningless.