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dissable interrupts with CPSR

Sebastian Gaertner
Note: This was originally posted on 19th June 2009 at http://forums.arm.com

Hi,

this regards the ARM 7 core.

In the CPSR register I can set the "I bit" to dissable the "IRQ interrupts" But which all interrupts does this mean, and which interrupts will remain active?
For example at the Cortex M3 there are high priority exceptions like
- BusFaultException
- HardFaultException


Does the ARM7 also have exceptions like this that is not covered by the "I bit"  ?
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  • Arm Employee Badge
    Note: This was originally posted on 19th June 2009 at http://forums.arm.com

    IRQ interrupts are interrupts wired to the IRQ input pin of the processor - typically via an interrupt controller. What interrupt sources are wired up to IRQ depends on the SoC design - but you are typically talking about peripheral devices such as timers, GPUs, crypto blocks, etc.

    ARM also supports FIQ (Fast Interrupt reQuest), which connect to the FIQ pin of the processor, also typically via an interrupt controller.

    Memory access errors such as BusFault are classified as "exceptions" rather than interrupts, and will typically cause the processor to see a data abort, or prefetch abort.
Reply
  • Arm Employee Badge
    Note: This was originally posted on 19th June 2009 at http://forums.arm.com

    IRQ interrupts are interrupts wired to the IRQ input pin of the processor - typically via an interrupt controller. What interrupt sources are wired up to IRQ depends on the SoC design - but you are typically talking about peripheral devices such as timers, GPUs, crypto blocks, etc.

    ARM also supports FIQ (Fast Interrupt reQuest), which connect to the FIQ pin of the processor, also typically via an interrupt controller.

    Memory access errors such as BusFault are classified as "exceptions" rather than interrupts, and will typically cause the processor to see a data abort, or prefetch abort.
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