Arm Development Studio forum dissable interrupts with CPSR

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dissable interrupts with CPSR

Note: This was originally posted on 19th June 2009 at http://forums.arm.com

Hi,

this regards the ARM 7 core.

In the CPSR register I can set the "I bit" to dissable the "IRQ interrupts" But which all interrupts does this mean, and which interrupts will remain active?
For example at the Cortex M3 there are high priority exceptions like
- BusFaultException
- HardFaultException

Does the ARM7 also have exceptions like this that is not covered by the "I bit" ?