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dissable interrupts with CPSR

Sebastian Gaertner
Note: This was originally posted on 19th June 2009 at http://forums.arm.com

Hi,

this regards the ARM 7 core.

In the CPSR register I can set the "I bit" to dissable the "IRQ interrupts" But which all interrupts does this mean, and which interrupts will remain active?
For example at the Cortex M3 there are high priority exceptions like
- BusFaultException
- HardFaultException


Does the ARM7 also have exceptions like this that is not covered by the "I bit"  ?
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  • Note: This was originally posted on 23rd June 2009 at http://forums.arm.com

    yes, BusFaultException and HardFaultException are IMHO only at M3 cortex.
    I thought that there are similar exceptions (with other names) at ARM7TDMI.


    Yes, there are memory abort, data abort etc. for ARM7TDMI but the interrupt mask bits in the CPSR affect only the interrupts..
    If you set the 'I' bit, normal interrupts (IRQ) will be masked ( disabled ) and if you set 'F' bit, fast interrupt (FIQ) will be masked..
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  • Note: This was originally posted on 23rd June 2009 at http://forums.arm.com

    yes, BusFaultException and HardFaultException are IMHO only at M3 cortex.
    I thought that there are similar exceptions (with other names) at ARM7TDMI.


    Yes, there are memory abort, data abort etc. for ARM7TDMI but the interrupt mask bits in the CPSR affect only the interrupts..
    If you set the 'I' bit, normal interrupts (IRQ) will be masked ( disabled ) and if you set 'F' bit, fast interrupt (FIQ) will be masked..
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