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Address Translation and Attributes

Samar Samar
Note: This was originally posted on 24th April 2009 at http://forums.arm.com

I have a memory section mapping as below:

______address_________|_physical_____________|_d_|_size____|_permissions________
____________|_glb|_shr|_access
__C:B0200000--B02FFFFF|__A:01E00000--01EFFFFF|_0F|_00100000|_P:readwrite_U:readwrite________|_yes|_no_|_write-through/buffered

The first level descriptor is at address 00A26C04
___address__|________0________4________8________
SD:00A26C00|                                    >01E00DEA    

Hence the physical address for B0200000 is 01E00000.
The Attributes are 0x00DEA.

C = 1
B = 0
XN = 0
domain (d) = 0xF
AP = 0x11
TEX = 0x000
Type = Section (1MB)

TEX (0x000) and CB (0x10) indicate cache policy of Outer and inner write through, no write allocate so my questions are:

1. What determines if it is buffered/non-buffered?
2. Is buffered/non-buffered referring to the use of write buffers?
3. What do inner and outer mean on the system that only have L1 cache?
4. If a memory region is shared between processors and its attributes are non-cache/buffered then do I have to perform data memory barrier operation after writing to any location in that region?

Thanks,
Samar
  • Note: This was originally posted on 24th April 2009 at http://forums.arm.com

    > 1. What determines if it is buffered/non-buffered?

    [url="http://arminfo/help/topic/com.arm.doc.ddi0333g/ch06s07s06.html"]arminfo/.../url]

    > 2. Is buffered/non-buffered referring to the use of write buffers?

    Yes.

    > 3. What do inner and outer mean on the system that only have L1 cache?

    L1 is always inner. You have no outer in your case. Note that caches more distant from the core are sometimes configured as "inner", but normally are "outer".

    > 4. If a memory region is shared between processors and its attributes are non-cache/buffered then do I have to perform data memory barrier operation after writing to any location in that region?

    It will "eventually" hit the external memory system. If you want to ensure it has been committed to the external memory before signaling the other processing device, then yes you will need a cache clean or clean+invalidate followed by a DMB.


    Hi Iso,

    The memory region is mapped as non-cache/buffered. So do i HAVE to do cache clean or clean+invalidate? You mentioned about cache cleaning and invalidating. I did not even think about that since it is marked as non-cache-able. But my original question is whether I need to do DMB or not to guarantee that the other processor sees the new value written?

    Also, that link for buffered/non-buffered question isnt working well for me. I dont know why. Can you point me to the base url and from there i can navigate to the required document?

    Thanks a lot for help.
    Samar
  • Arm Employee Badge
    Note: This was originally posted on 26th April 2009 at http://forums.arm.com

    Hi Samar,

    No you won't need a cache clean and invalidate for uncached-buffered, but as you say may need a DMB to ensure that the write buffer has drained before signalling the other processor.

    I've fixed the link in my original post,

    Iso
  • Arm Employee Badge
    Note: This was originally posted on 24th April 2009 at http://forums.arm.com

    > 1. What determines if it is buffered/non-buffered?

    [url="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0333g/ch06s07s06.html"]http://infocenter.arm.com/help/index.jsp?t...ch06s07s06.html[/url]

    > 2. Is buffered/non-buffered referring to the use of write buffers?

    Yes.

    > 3. What do inner and outer mean on the system that only have L1 cache?

    L1 is always inner. You have no outer in your case. Note that caches more distant from the core are sometimes configured as "inner", but normally are "outer".

    > 4. If a memory region is shared between processors and its attributes are non-cache/buffered then do I have to perform data memory barrier operation after writing to any location in that region?

    It will "eventually" hit the external memory system. If you want to ensure it has been committed to the external memory before signaling the other processing device, then yes you will need a cache clean or clean+invalidate followed by a DMB.