• State Suggested Answer
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 121 subscribers
  • Views 3525 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cannot read/write interval timer register DE1-SoC HPS

Red2503

I have a DE1-SoC  (Cyclone V) board where I am trying to get timer interrupts to work on the HPS. I found an example in the Intel FPGA University Program called "interrupt_example", and when I run it on the Intel FPGA Universioty Program, it runs perfectly.

Now I want to transfer this project to ARM DS, but I cannot get it to work because everytime when I am trying to write to the interval timer at address 0xFF202000, the debugger won't proceed. When I try to look in the memory of 0xFF202000 in ARM DS, I also cannot see anything.


I am using the same compiler (GCC C 4.7.3 arm-altera-eabi) and I tried to use the same compiler arguments:

 

Intel FPGA Monitor Program

rm -f interrupt_example.c.o
arm-altera-eabi-gcc -Wall -c -g -O1 -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 interrupt_example.c -o interrupt_example.c.o
rm -f exceptions.c.o
arm-altera-eabi-gcc -Wall -c -g -O1 -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 exceptions.c -o exceptions.c.o
rm -f HPS_timer_ISR.c.o
arm-altera-eabi-gcc -Wall -c -g -O1 -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 HPS_timer_ISR.c -o HPS_timer_ISR.c.o
rm -f interval_timer_ISR.c.o
arm-altera-eabi-gcc -Wall -c -g -O1 -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 interval_timer_ISR.c -o interval_timer_ISR.c.o
rm -f pushbutton_ISR.c.o
arm-altera-eabi-gcc -Wall -c -g -O1 -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 pushbutton_ISR.c -o pushbutton_ISR.c.o
rm -f interrupt_example.axf

 

ARM DS

make all
'Building file: ../interrupt_example/HPS_timer_ISR.c'
'Invoking: GCC C Compiler 4.7.3 [arm-altera-eabi]'
arm-altera-eabi-gcc.exe -Dsoc_cv_av -I"C:\CSA\Baremetal_Hex_Disco\sw\hps\application\inc" -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -O1 -g3 -Wall -c -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 -MMD -MP -MF"interrupt_example/HPS_timer_ISR.d" -MT"interrupt_example/HPS_timer_ISR.o" -c -o "interrupt_example/HPS_timer_ISR.o" "../interrupt_example/HPS_timer_ISR.c"
'Finished building: ../interrupt_example/HPS_timer_ISR.c'
' '
'Building file: ../interrupt_example/exceptions.c'
'Invoking: GCC C Compiler 4.7.3 [arm-altera-eabi]'
arm-altera-eabi-gcc.exe -Dsoc_cv_av -I"C:\CSA\Baremetal_Hex_Disco\sw\hps\application\inc" -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -O1 -g3 -Wall -c -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 -MMD -MP -MF"interrupt_example/exceptions.d" -MT"interrupt_example/exceptions.o" -c -o "interrupt_example/exceptions.o" "../interrupt_example/exceptions.c"
'Finished building: ../interrupt_example/exceptions.c'
' '
'Building file: ../interrupt_example/interval_timer_ISR.c'
'Invoking: GCC C Compiler 4.7.3 [arm-altera-eabi]'
arm-altera-eabi-gcc.exe -Dsoc_cv_av -I"C:\CSA\Baremetal_Hex_Disco\sw\hps\application\inc" -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -O1 -g3 -Wall -c -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 -MMD -MP -MF"interrupt_example/interval_timer_ISR.d" -MT"interrupt_example/interval_timer_ISR.o" -c -o "interrupt_example/interval_timer_ISR.o" "../interrupt_example/interval_timer_ISR.c"
'Finished building: ../interrupt_example/interval_timer_ISR.c'
' '
'Building file: ../interrupt_example/pushbutton_ISR.c'
'Invoking: GCC C Compiler 4.7.3 [arm-altera-eabi]'
arm-altera-eabi-gcc.exe -Dsoc_cv_av -I"C:\CSA\Baremetal_Hex_Disco\sw\hps\application\inc" -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -O1 -g3 -Wall -c -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 -MMD -MP -MF"interrupt_example/pushbutton_ISR.d" -MT"interrupt_example/pushbutton_ISR.o" -c -o "interrupt_example/pushbutton_ISR.o" "../interrupt_example/pushbutton_ISR.c"
'Finished building: ../interrupt_example/pushbutton_ISR.c'
' '
'Building file: ../.metadata/.plugins/org.eclipse.cdt.make.core/specs.c'
'Invoking: GCC C Compiler 4.7.3 [arm-altera-eabi]'
arm-altera-eabi-gcc.exe -Dsoc_cv_av -I"C:\CSA\Baremetal_Hex_Disco\sw\hps\application\inc" -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -O1 -g3 -Wall -c -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 -MMD -MP -MF".metadata/.plugins/org.eclipse.cdt.make.core/specs.d" -MT".metadata/.plugins/org.eclipse.cdt.make.core/specs.o" -c -o ".metadata/.plugins/org.eclipse.cdt.make.core/specs.o" "../.metadata/.plugins/org.eclipse.cdt.make.core/specs.c"
'Finished building: ../.metadata/.plugins/org.eclipse.cdt.make.core/specs.c'
' '
'Building file: ../main.c'
'Invoking: GCC C Compiler 4.7.3 [arm-altera-eabi]'
arm-altera-eabi-gcc.exe -Dsoc_cv_av -I"C:\CSA\Baremetal_Hex_Disco\sw\hps\application\inc" -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -O1 -g3 -Wall -c -mfloat-abi=soft -march=armv7-a -mtune=cortex-a9 -mcpu=cortex-a9 -MMD -MP -MF"main.d" -MT"main.o" -c -o "main.o" "../main.c"
'Finished building: ../main.c'
' '

I am also using the same linker arguments:


Intel FPGA Monitor Program

arm-altera-eabi-gcc -Wl,--defsym -Wl,arm_program_mem=0x40 -Wl,--defsym -Wl,arm_available_mem_size=0x3fffffb8 -Wl,--defsym -Wl,__cs3_stack=0x3ffffff8 -Wl,--section-start -Wl,.vectors=0x0 -T"C:/intelFPGA_lite/17.0/University_Program/Monitor_Program/build/altera-socfpga-hosted-with-vectors.ld" interrupt_example.c.o exceptions.c.o HPS_timer_ISR.c.o interval_timer_ISR.c.o pushbutton_ISR.c.o -o interrupt_example.axf

 

ARM DS

arm-altera-eabi-gcc -T "C:\intelFPGA_lite\17.0\University_Program\Monitor_Program\build\altera-socfpga-hosted-with-vectors.ld" --exceptions -Wl,--defsym -Wl,arm_program_mem=0x40 -Wl,--defsym -Wl,arm_available_mem_size=0x3fffffb8 -Wl,--defsym -Wl,__cs3_stack=0x3ffffff8 -Wl,--section-start -Wl,.vectors=0x0 -o "Baremetal_Hex_Disco.axf" ./interrupt_example/HPS_timer_ISR.o ./interrupt_example/exceptions.o ./interrupt_example/interval_timer_ISR.o ./interrupt_example/pushbutton_ISR.o ./.metadata/.plugins/org.eclipse.cdt.make.core/specs.o ./main.o


I also tried to use the same preloader, but this does not work out when I am writing the debug script. I am not sure if this is the problem. If this is actually the problem, I would appreciate it if someone can help me writing another debug script, because ARM DS is giving me problems when I try to use u-boot-spl.de1-soc.srec as a preloader.

 

Preloader information in Intel FPGA Monitor Program

Info: Running Quartus Prime Programmer
Info: Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
Info: Copyright (C) 2017 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Intel and sold by Intel or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Sun Feb 07 10:04:39 2021
Info: Command: quartus_hps --cable="DE-SoC [USB-1]" -o GDBSERVER --gdbport0=3350 --preloader=C:/intelFPGA_lite/17.0/University_Program/Monitor_Program/arm_tools/u-boot-spl.de1-soc.srec --preloaderaddr=0xffff13a0 --source=C:/Users/red25/Documents/interrupt_example.srec
Current hardware is: DE-SoC [USB-1]
Successfully change hardware frequency to 16Mhz
Found HPS at device 1
Double check JTAG chain
HPS Device IDCODE: 0x4BA00477
AHB Port is located at port 0
APB Port is located at port 1
Double check device identification ...
>>CPU0 halted at 0x2fa8.
>>Resetting HPS.
>>Downloading preloader.....
>>Program loaded. PC set to program entry (0xFFFF0000)
>>Setting vector base address register to: 0xffff0000
>>Running preloader..
>>Preloader successfully run.
>>Downloading user program.
>>Program loaded. PC set to program entry (0x0128)
>>Setting vector base address register to: 0x0
>> Hard breakpoint set.
Starting GDB Server.

 

Debug script in ARM DS

reset
wait 5s
stop
wait
loadfile "$sdir/../../preloader/uboot-socfpga/spl/u-boot-spl" 0x0
set semihosting enabled true
delete
tbreak spl_boot_device
run
wait
loadfile "$sdir/../Debug/Baremetal_Hex_Disco.axf" 0x0
start

 

The disassembly of the code where the 0xFF202000 is being written also looks identical:

Intel FPGA Monitor Program

 

ARM DS

 

I tried everything which I could think of now. I really hope someone can help me. Thank you in advance.

Parents
  • 0

    Hi, my name is Stephen and I work for Arm.

    I'm not very familiar with the Cyclone V board, but I might be offer some general debugging suggestions.

    You wrote:
    >When I am trying to write to the interval timer at address 0xFF202000, the debugger won't proceed.

    Can you explain what you mean by "the debugger won't proceed"?  Are you setting a breakpoint on config_interval_timer(), running to the breakpoint successfully, then single-stepping through its instructions?  At which instruction does code execution stop proceeding as expected?  Is a data abort exception occurring on the STR to address 0xFF202000 + 8 ?

    >When I try to look in the memory of 0xFF202000 in ARM DS, I also cannot see anything.

    In general, you should avoid using the Arm DS GUI Memory view to access volatile or read-sensitive peripheral registers, because the Memory view might read from a wider range of addresses, re-read that area multiple times, or cache values that it has read.  Use the CLI instead, e.g:

    output /x *0xFF202008

    Hope this helps

Reply
  • 0

    Hi, my name is Stephen and I work for Arm.

    I'm not very familiar with the Cyclone V board, but I might be offer some general debugging suggestions.

    You wrote:
    >When I am trying to write to the interval timer at address 0xFF202000, the debugger won't proceed.

    Can you explain what you mean by "the debugger won't proceed"?  Are you setting a breakpoint on config_interval_timer(), running to the breakpoint successfully, then single-stepping through its instructions?  At which instruction does code execution stop proceeding as expected?  Is a data abort exception occurring on the STR to address 0xFF202000 + 8 ?

    >When I try to look in the memory of 0xFF202000 in ARM DS, I also cannot see anything.

    In general, you should avoid using the Arm DS GUI Memory view to access volatile or read-sensitive peripheral registers, because the Memory view might read from a wider range of addresses, re-read that area multiple times, or cache values that it has read.  Use the CLI instead, e.g:

    output /x *0xFF202008

    Hope this helps

Children
No data