I am trying to develop an app that requires the communication between two cores. My question is, I have built two different images for two different cores (Cortex-M3 and Cortex-M4) in axf format. I also have FVP model that includes two cores (Cortex-M3 and Cortex-M4). My question is if I can use DS-5 debugger to run the two images (axf file) and debug them after I import the FVP model to DS-5?
Thank you for your input in advance.
I don't think there's any reason why you couldn't establish two connections in DS-5 Debugger. I'm assuming that you used Fast Models to build your Cortex-M3/M4 platform?
For a tutorial on importing models into DS-5: Importing models into DS-5 | ARM DS-5 Development Studio
Hope this helps,
Joe
Hi Joe,
Thank you very much for your reply. You are right, I can establish two connections in DS-5 debugger. But, each connection is run one at a time, what I mean is they cannot be run in parallel as real two-core system does. I am doing something like inter-core communication. So, the timing will be off by running one core first and the other core second. I am not sure if I make myself clear. By using the debugger, some real cases cannot be reproduced. Do you agree?
Regards,
Shulan
Hi Shulan,
Thanks for the extra info. I advise that you contact technical support so that they can work through your setup. Depending on what you're trying to achieve, it might turn out to be easier to use Keil MDK.
Thanks,
Hi Shulan
Sorry for late reply - you may have already resolved this.
You are right that we don't yet have a mechanism to simultaneously start both connections, but I've hacked together a pseudo solution for this in the past.
In your code for Core0, just after main, have a while loop waiting for an (shared) address to be written to (by Core1). Load this code and go, it will be stuck in this while loop.
Then in your code for Core1, again just after main, write to the above shared address - from there both CPUs will continue on from that point.
Note that the FVPs are not timing accurate, so you will never be able to accurately model cycle for cycle behavior with these models.
Regards
Ronan
Hi, Ronan,
Thank you very much for your reply. That makes sense to to use shared memory to sync two cores. I mean it is a way to do it.
I understand FVP timing is not accurate. I am wondering how about relative performance comparison, is it enough to judge the quality of model. For instance, there are two slightly different designs, would it make sense to compare their FVP performance to determine which design is better?
Best Regards,
FVPs are not really suitable for performance analysis. The best you can get is a comparison of number of instructions, but if running the same code on two different designs, this should be the same. It won't take into account any bus traffic roadblocks etc.
You could consider the MPS2 board, which allows you to build an FPGA image of your system. This won't help with the multi-core system in your case.
Sorry I don't have a single perfect answer :-(