freeRTOS demo DS-5 ERROR(CMD360) when trying to debug

Hello, I believe you have the same issue as reported on the Intel forum below:
https://community.intel.com/t5/Nios-II-Embedded-Design-Suite/DS-5-Baremetal-Failed-to-load-image/td-p/138277

The solution mentioned there is to manually enable semihosting:

set semihosting enabled true

Hello, I believe you have the same issue as reported on the Intel forum below:
https://community.intel.com/t5/Nios-II-Embedded-Design-Suite/DS-5-Baremetal-Failed-to-load-image/td-p/138277

The solution mentioned there is to manually enable semihosting:

set semihosting enabled true

Thank you.  That does seem to be  one of the issues I am having.  I believe I corrected it but now still have an issue with:

Starting target with image D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\uboot-socfpga\spl\u-boot-spl
Running from entry point
Execution stopped in SVC mode at S:0xFFFF0000

In start.S
Unable to read source file D:/SJ/nightly/14.0/200/w64/acds/embedded/examples/hardware/av_soc_devkit_ghrd/software/preloader/uboot-socfpga/arch/arm/cpu/armv7/start.S

which was in my error log but not the original poster's output.

The "Unable to read source file" message is displayed because the elf file that was loaded (D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\uboot-socfpga\spl\u-boot-spl) includes symbols and knows the path/filenames of the original files used to compile the elf image.  

You can safely ignore this message.  It is not an error.  It is mentioning that it cannot find the source assembly/C file(s) associated with the current address of the breakpoint.  This is usually ok, in this case, since you want to stop the preloader at a safe place, then load the rest of the code.  You usually don't need to debug or step through the source in start.S. 

You can also download all the source code for the preloader, and provide path substitutions in the GUI to the location of the start.S (and the rest of the preloader source), but it is likely not needed. 

Here is more information on the path substitution used in both Arm DS and DS-5:

https://developer.arm.com/documentation/dui0446/v/controlling-execution/configuring-the-debugger-path-substitution-rules

Thanks for the response.  It seems like I was mistaken that I solved the original problem then.  After adding the line "set semihosting enabled 1" in the preloader.ds I get the same errors with some additional ones now.

Stopping running target Intel SoC FPGA - Cyclone V SoC (Dual Core) on connection
Connected to running target Intel SoC FPGA - Cyclone V SoC (Dual Core)
Execution stopped in SVC mode at S:0xFFFF446C
S:0xFFFF446C   B        {pc} ; 0xffff446c
cd "D:\UserData\z0045mwh\Documents\DS-5 Workspace"
Working directory "D:\UserData\z0045mwh\Documents\DS-5 Workspace"
Execution stopped in SVC mode at S:0xFFFF446C
S:0xFFFF446C   B        {pc} ; 0xffff446c
source /v "C:\intelFPGA\18.1\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check.py"

No SYSID registers could be found. Has a peripheral description file been supplied?

source /v "D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\preloader.ds"
+stop
WARNING(CMD315): Target is not running
+wait 5s
+reset system
+wait 5s
+loadfile "$sdir/uboot-socfpga/spl/u-boot-spl" 0x0
Loaded section .text: S:0xFFFF0000 ~ S:0xFFFF671B (size 0x671C)
Loaded section .rodata: S:0xFFFF671C ~ S:0xFFFF82E4 (size 0x1BC9)
Loaded section .data: S:0xFFFF82E8 ~ S:0xFFFF91AF (size 0xEC8)
Entry point S:0xFFFF0000
Target has been reset
Execution stopped in SVC mode at S:0xFFFF446C
Unable to read source file D:/SJ/nightly/14.0/200/w64/acds/embedded/examples/hardware/av_soc_devkit_ghrd/software/preloader/uboot-socfpga/common/spl/spl.c
S:0xFFFF446C   56,0   B        hang+8 ; 0xFFFF446C
+set semihosting enabled 1
Semihosting server socket created at port 8001
+set debug-from *$entrypoint     # Set start-at setting to address of $entrypoint
+start
Reloading program
Starting target with image D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\uboot-socfpga\spl\u-boot-spl
Running from entry point
Execution stopped in SVC mode at S:0xFFFF0000
In start.S
Unable to read source file D:/SJ/nightly/14.0/200/w64/acds/embedded/examples/hardware/av_soc_devkit_ghrd/software/preloader/uboot-socfpga/arch/arm/cpu/armv7/start.S
S:0xFFFF0000   39,0   B        reset ; 0xFFFF0070
+delete
All user breakpoints deleted
+tbreak spl_boot_device
Breakpoint 2 at S:0xFFFF110C
    on file spl.c, line 70
    on file spl.c, line 80
+cont
+wait 60s
ERROR(CMD360):
# in D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\preloader.ds:49 while executing: wait 60s
! Wait for stopped timed out
ERROR(CMD656): The script D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\preloader.ds failed to complete due to an error during execution of the script
loadfile "D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\Debug\RTOSDemo.elf"
ERROR(CMD16-TAD11-NAL22):
! Failed to load "RTOSDemo.elf"
! Failed to write 8 bytes to address S:0x0011B754
! General error on memory or register access.
ERROR(COR118-TAD1-NAL52):
! Unable to determine if stopped for semihosting
! Unable to read from register SPSR_UND
! Cannot attain state requested.
Execution stopped in UND mode at S:0xFFFF0004
Unable to read source file D:/SJ/nightly/14.0/200/w64/acds/embedded/examples/hardware/av_soc_devkit_ghrd/software/preloader/uboot-socfpga/arch/arm/cpu/armv7/start.S
ERROR(CMD256-TAD10-NAL52):
! Unable to display contents at location "S:0xFFFF0004"
! Failed to read 4 bytes from address S:0xFFFF0004
! Cannot attain state requested.
set debug-from main
start
WARNING(CMD399-COR168):
! Failed to start the target
! No function named "main" could be found
WARNING(CMD407): Trying the entry point instead
ERROR(CMD399-CMD27-TAD1-NAL52):
! Failed to start the target
! Failed to set a breakpoint
! Unable to read from register SP
! Cannot attain state requested.
wait
ERROR(TAD1-NAL52):
! Unable to read from register SP
! Cannot attain state requested.
Target Message: Could not determine target state
Target Message: Could not determine target state
Target Message: Could not determine target state
Target Message: Could not determine target state
Target Message: Could not determine target state

Any insight is greatly appreciated.

Is it possible to share this script? I don't know what exactly it does.

Making an educated guess - it is initializing memory, but in your case, it takes more than 60 seconds (the CMD360 error), which tells me that something went wrong with that stage - then it tries to load the ELF file to this address, which therefore fails?

Here is the preloader.ds script

############################################################
#
# Copyright Altera 2013
# All Rights Reserved
# File: preloader.ds
#
############################################################

#
# stop processor if running
#
stop
wait 5s
reset system
wait 5s

#set semihosting enabled 

#
# load the preloader (a.k.a the spl from our uboot dist)
#
loadfile "$sdir/uboot-socfpga/spl/u-boot-spl" 0x0

set semihosting enabled 1


#
# set pc to entry point
#
set debug-from *$entrypoint     # Set start-at setting to address of $entrypoint
start 

#
# delete any breakpoints
#
delete

#
# set hw breakpoint in spl in function, spl_boot_device,
# The function, spl_boot_device, is called right before the spl tries
# to load.  We stop here so we don't have to change any spl.
#
tbreak spl_boot_device

# tell target to continue executing spl
cont

# wait for breakpoint
wait 60s

I'm basically trying to follow these steps but on a different Cyclone V development board. I've updated the application code to control a GPIO that's connected to an LED on this board.

https://www.freertos.org/RTOS_Altera_SoC_ARM_Cortex-A9.html#build_instructions

Also, you might be able to find answers directly from Intel, since Altera (now Intel) originally created the ds scripts above.  Their Embedded forum can be found here:

https://community.intel.com/t5/Intel-SoC-FPGA-Embedded/bd-p/soc-fpga-embedded-development-suite

There are also example designs included with SoCEDS. These containother scripts that might be useful.  These can be found here:

https://fpgasoftware.intel.com/soceds/

any thoughts now that the script is included?

thanks for the reference.  I also posted a question over there as well.

Hi again,

Sorry, I can't think of anything detailed to add - the script sets a breakpoint at "spl_boot_device" that is never hit, the script times out after 60 seconds.

Perhaps try manually performing each step of the script, or set additional breakpoints - do you ever reach main()?