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Get missing source data $Cache Data Refill / $Cache DataAccess in streamline

Olfat

Hello every one,

I'm using ARM DS-5 (DS-5 Community Edition) Version: 5.17.1 stream line to analyse  my Samsung galaxy Nexus maguro with customize factory img yakju-jwr66y to work with streamline.

when i analyse the data i  can not get info about the cache it gives me the error ds-5 streamline cache l1 refill missing source data $Cache Data Refill / $Cache DataAccess

i really need to get the number of hits and missed to the cache in order to now the bandwidth used by each program running into my system so i would appreciate your help.

Thanks

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  • 0 in reply to Peter Harris

    Hello Peter,

    I was looking for a solution to an issue I am facing and found this post. In your response- "Note you'll probably want to use the L2 cache counters, rather than the L1 data cache counters if you want system memory bandwidth". Can you please elaborate on using L2 cache counters v/s L1 counters. I notice that the L1 Data Refills are not same as L2 Data requests, in fact they are twice that number. I am unable to understand why. I am using a Exynos4 Quad 4412 that has PL 310 L2 Controller. My application mostly does Loads from L2 Cache. So, most of the Loads miss L1 Data cache. Could the increase in L2 Data requests be due to other non-core modules accessing L2 cache?

    Thanks,

    DK

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  • 0 in reply to Peter Harris

    Hello Peter,

    I was looking for a solution to an issue I am facing and found this post. In your response- "Note you'll probably want to use the L2 cache counters, rather than the L1 data cache counters if you want system memory bandwidth". Can you please elaborate on using L2 cache counters v/s L1 counters. I notice that the L1 Data Refills are not same as L2 Data requests, in fact they are twice that number. I am unable to understand why. I am using a Exynos4 Quad 4412 that has PL 310 L2 Controller. My application mostly does Loads from L2 Cache. So, most of the Loads miss L1 Data cache. Could the increase in L2 Data requests be due to other non-core modules accessing L2 cache?

    Thanks,

    DK

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