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Invalidating Cache Lines

Note: This was originally posted on 25th July 2013 at http://forums.arm.com

Hi

I'm trying to invalidate specific areas of the data caches (L1 and L2) on a dual A9 architecture (Zynq 7000). Looking specifically at the L1 cache, some sample code I have suggests:


  for(all affected cache lines)
  {
    MCR p15 DCIMVAC cacheLine
    dsb
 }

This is slow

.

I wondered if the dsb is needed between every MCR? Could I just do:


  for(all affected cache lines)
  {
    MCR p15 DCIMVAC cacheLine
  }
  dsb

I noted 'A.1.6. Delayed operation of CP15 instructions' in the 'Fast Models Reference Manual' but I'm having trouble tracking down information on sequential operations on the same coprocessor register.

Also... does anyone have any better cache-range invalidation methods?

Cheers

Joe

Joe Skaife over 12 years ago

Note: This was originally posted on 25th July 2013 at http://forums.arm.com

Brilliant! Thank you Iso!

Joe
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Peter Harris over 12 years ago

Note: This was originally posted on 25th July 2013 at http://forums.arm.com

Hi Joe,

Your second code should be fine. You only need the dsb when you want to guarantee that the cache flush has finished/hit memory, so doing it after the whole flush is fine.

HTH,
Iso
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Michael Pulice over 11 years ago in reply to Joe Skaife

Any idea what happened to the answer from the original forum? I am interested in what Iso replied.
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Peter Harris over 11 years ago in reply to Michael Pulice

Iso was me - the account names got changed to match the new user accounts when we imported things across to the Community site, and the ordering became mixed slightly. So the original answer is the post below.
HTH,
Pete
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