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Cortex series scheme NEON has rename SIMD register?

Lee Jesse
Note: This was originally posted on 18th April 2013 at http://forums.arm.com

NEON contains 16 SIMD user visible registers q0~q15, while does it have more architecturally visible register? Just like general 32 bit register engaged.
Anybody know which document or spec demonstrate related topic?
Thanks to any interesting discussion!
  • Note: This was originally posted on 19th April 2013 at http://forums.arm.com

    Thanks for your informational reply!
    I"˜m inclined of opinion that even certified vendor redesign A15 microarchitecture to generate their own A15( like Qualcom or Apple), the arm official spec ( figure like queue/window size) still provided partly the minimize reference figure. Right?
    And can you prefer to let me know which keyword you used to search and found the pdf?
    I had tried "Cortex micro architecture " before I posed this topic, but found only A9 whitepaper.
    Thanks again!
  • Note: This was originally posted on 19th April 2013 at http://forums.arm.com

    CPU designs from Qualcomm and Apple are completely independent of CPU designs from ARM like Cortex-A15. They're designed to meet the architecture spec (ARMv7a) but this has no constraints in implementation details like instruction reordering. Just that the instruction semantics have to be correct.

    Neither company says very much about their CPUs, I don't think Apple has even publicly mentioned they made one at all.

    Look at page 24 of the PDF I linked, it talks about register renaming there.
  • Note: This was originally posted on 18th April 2013 at http://forums.arm.com

    NEON on Cortex-A5, A7, A8, and A9 has no register renaming.

    NEON on Cortex-A15 has register renaming and can be executed out of order (http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf). I can't find any references as to how large the result queue or rename tables are.