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Configuring ARM Trace for dumping into System Memory?

rugger 123
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Note: This was originally posted on 9th March 2013 at http://forums.arm.com

Hi,

I am working on Cortex A8 processor using openocd and want to configure the trace to dump into the system memory. I went through the reference manuals and enabled trace (ETM) , and configured CSTF and ETF but still I am unable to configure the trace completely. I can list the steps in detail if required. Is there any document where I can get the exact configuration of all these components?

Thanks,
R.
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    Note: This was originally posted on 19th March 2013 at http://forums.arm.com

    Hi,

    If you want to store trace directly to system memory, then you will need to use the Embedded Trace Router (ETR) configuration of the CoreSight Trace Memory Controller (TMC).  The ETR provides an ATB slave interface, so that it can receive trace from your trace subsystem, and an AXI master interface, so that it can route data to an AXI slave interface.  You could integrate some dedicated DRAM (via a DMC), or you could connect the ETR to a shared or dedicated interconnect.  Remember that if you connect the ETR AXI i/f to a shared interconnect, then bandwidth is shared with the other masters - i.e. you will affect the system performance, and also create contention for ETR trace data going to memory.

    The alternative is to make use of the Embedded Trace Buffer (either the CoreSight ETB, or the ETB configuration of the TMC), so that you can store trace data to dedicated SRAM.  You could then use a system master to copy the data from the ETB SRAM to some system memory.

    For programming information, see the CoreSight Components TRM (original CoreSight components), the CoreSight SoC TRM (CoreSight SoC components) and the Trace Memory Controller TRM (TMC).

    Best regards,

    Richard
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  • Offline
    Note: This was originally posted on 19th March 2013 at http://forums.arm.com

    Hi,

    If you want to store trace directly to system memory, then you will need to use the Embedded Trace Router (ETR) configuration of the CoreSight Trace Memory Controller (TMC).  The ETR provides an ATB slave interface, so that it can receive trace from your trace subsystem, and an AXI master interface, so that it can route data to an AXI slave interface.  You could integrate some dedicated DRAM (via a DMC), or you could connect the ETR to a shared or dedicated interconnect.  Remember that if you connect the ETR AXI i/f to a shared interconnect, then bandwidth is shared with the other masters - i.e. you will affect the system performance, and also create contention for ETR trace data going to memory.

    The alternative is to make use of the Embedded Trace Buffer (either the CoreSight ETB, or the ETB configuration of the TMC), so that you can store trace data to dedicated SRAM.  You could then use a system master to copy the data from the ETB SRAM to some system memory.

    For programming information, see the CoreSight Components TRM (original CoreSight components), the CoreSight SoC TRM (CoreSight SoC components) and the Trace Memory Controller TRM (TMC).

    Best regards,

    Richard
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