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Configuring ARM Trace for dumping into System Memory?

rugger 123
Note: This was originally posted on 9th March 2013 at http://forums.arm.com

Hi,

I am working on Cortex A8 processor using openocd and want to configure the trace to dump into the system memory. I went through the reference manuals and enabled trace (ETM) , and configured CSTF and ETF but still I am unable to configure the trace completely. I can list the steps in detail if required. Is there any document where I can get the exact configuration of all these components?

Thanks,
R.
  • Note: This was originally posted on 27th March 2013 at http://forums.arm.com

    Hey,

    Thanks Richard for the detailed answer. I have gone through all  the TRMs extensively and tried to understand about the tracing. I went through the programming models to configure each component. I was able to understand whatever you had told in your post. Let me tell about the problem i'm facing. Basically I want to configure the entire trace to be stored in the system memory. I just want to first get the flow of the configurations correct.

    1) I programmed the ETM and enabled few triggers of trace between some address segment.
    2) I programmed the coresight funnel to enable the trace channels.
    3) I programmed the ETF to drain the trace through the ATB slave interface.
    4) I programmed the ETR and configured the system address where the trace has to be stored.

    I thought I had made everything ready for the trace and ran the execution of some code.

    But I didnot get any trace output stored in the memory.!!
    First I want to know if whatever  I have done is correct? Am i missing something??

    Since there is not much of resources available on the net apart from the TRM , I find it difficult. Let me know if you find any mistake in my configurations.

    Thanks,
    R.
  • Note: This was originally posted on 19th March 2013 at http://forums.arm.com

    Hi,

    If you want to store trace directly to system memory, then you will need to use the Embedded Trace Router (ETR) configuration of the CoreSight Trace Memory Controller (TMC).  The ETR provides an ATB slave interface, so that it can receive trace from your trace subsystem, and an AXI master interface, so that it can route data to an AXI slave interface.  You could integrate some dedicated DRAM (via a DMC), or you could connect the ETR to a shared or dedicated interconnect.  Remember that if you connect the ETR AXI i/f to a shared interconnect, then bandwidth is shared with the other masters - i.e. you will affect the system performance, and also create contention for ETR trace data going to memory.

    The alternative is to make use of the Embedded Trace Buffer (either the CoreSight ETB, or the ETB configuration of the TMC), so that you can store trace data to dedicated SRAM.  You could then use a system master to copy the data from the ETB SRAM to some system memory.

    For programming information, see the CoreSight Components TRM (original CoreSight components), the CoreSight SoC TRM (CoreSight SoC components) and the Trace Memory Controller TRM (TMC).

    Best regards,

    Richard
  • Note: This was originally posted on 15th March 2013 at http://forums.arm.com

    Hi,

    I have the same problem right now. I will use CoreSight component in a7/a15, but still not sure about the configuration the whole system to dump the trace information. So far as i see,  configure the ETM, CSTF and ETF should be enough to do dump test, what is the problem you met? Do you solve it?

    Since in our group, the ASIC team is working on hardware frame, i am preparing the test for them. If anyone can give some advice, please help.

    Best regards