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ARM7TDMI processor mode

shan S
Note: This was originally posted on 23rd November 2012 at http://forums.arm.com

I am using the ATMEL91SAM7SE512 controller with ARM7TDMI processor.The application is running in the User mode .

when the interrupt(IRQ) occurs processor must switch to IRQ mode,then it should go to the IRQ handler routine.

here application developer part is to tell the IRQ handler address only.so who taking the responsibility to change from User mode to IRQ mode.

whether the core itself switched into IRQ mode using hardware setup or some low level routines(program) avail.i struck in this point , i cant

proceed further on this study of ARM7TDMI processor.


please tell me your thoughts regarding this query.

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thanks
shan.s



Parents
  • Note: This was originally posted on 26th November 2012 at http://forums.arm.com


    I'd highly recommend the ARM System Developer's Guide book if you are interested in any of this low level platform setup; I always a copy open on my desk!



    Hi,
         I am really confused in the below mentioned thing.

    Let take
    Current Mode     = User mode;
    Exception occur = IRQ;

    Exception entry:
                when the IRQ occurs , have to copy the CPSR of user mode(current) to SPSR_irq.
    load the PC with irq exception vector address and load the return address of the User
    program into LR_irq.then we have to change the mode in the CPSR.

    Exception leaving:
               On leaving , have to copy the PC with the LR_irq and change the mode the CPSR to User mode.


    doubts in Exception entry:
    =====================

    1. Here they are accessing the SPSR_irq before moving the processor to the IRQ mode.
    How this is possible.because in user mode it is not possible  access the SPSR registers of
    other exception modes.
    2. i think the address value of  CPSR = 16.what is the address value of SPSR(irq,fiq,svr.....).

               can i get the any PDF of  ARM System Developer's Guide book .author name pls.


    thanks
    shan.s







Reply
  • Note: This was originally posted on 26th November 2012 at http://forums.arm.com


    I'd highly recommend the ARM System Developer's Guide book if you are interested in any of this low level platform setup; I always a copy open on my desk!



    Hi,
         I am really confused in the below mentioned thing.

    Let take
    Current Mode     = User mode;
    Exception occur = IRQ;

    Exception entry:
                when the IRQ occurs , have to copy the CPSR of user mode(current) to SPSR_irq.
    load the PC with irq exception vector address and load the return address of the User
    program into LR_irq.then we have to change the mode in the CPSR.

    Exception leaving:
               On leaving , have to copy the PC with the LR_irq and change the mode the CPSR to User mode.


    doubts in Exception entry:
    =====================

    1. Here they are accessing the SPSR_irq before moving the processor to the IRQ mode.
    How this is possible.because in user mode it is not possible  access the SPSR registers of
    other exception modes.
    2. i think the address value of  CPSR = 16.what is the address value of SPSR(irq,fiq,svr.....).

               can i get the any PDF of  ARM System Developer's Guide book .author name pls.


    thanks
    shan.s







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