• Locked Locked
  • Replies 3 replies
  • Subscribers 119 subscribers
  • Views 4193 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

LDREX fails after MMU is enabled on Beagleboard xM

Robbie VanVossen
Note: This was originally posted on 30th October 2012 at http://forums.arm.com

I am attempting to port a build of xen-arm to work for the Beagleboard xM. This board uses TI's DM3730 processor, which is built on a Cortex A8 r3p2. My issue is that once the MMU is enabled, LDREX (and presumably STREX) instructions fail. I get a data abort exception when the LDREX instruction executes.

I know that the processor supports the LDREX/STREX instructions. The exclusive instruction support bits, [23:20], of c0, Instruction Set Attributes Register 4 is the expected 0x0. I also tested using LDREX before enabling the MMU and it doesn't cause an exception.


Setup:
Text is loaded to 0x8030_8000

Page Table:
Written from 0x8030_4000 to 0x8030_7FFF.
I am performing a 1 to 1 mapping at 0x8000_0000 for 1024 MB. The section descriptor format I am using is 0x8001_15EE + current page, where current page is 0x10_0000 to 0x4000_0000.
These values should give the following configuration:
Uses Sections
Bufferable: 1
Cacheable: 1
Execute-Never: 0
Domain: 0xF = Domain 15
Access Permissions[1:0]: 0x01
Access Permissions X: 0
Shareable: 1
Not Global: 0
Non-Secure: 0

Translation Table Base Registers (0,1) c1,c0, {0,1}:
0x8000_400B
This gives the following configuration:
Not Outer Shareable: 0  (Not Implemented SBZP)
Cacheable: 1
Shareable: 1
Region Bits: 0x1  = Normal memory, Outer Write-Back Write-Allocate Cacheable

Coprocessor Access Control Register c1,c0,2:
0x000F_0000
This gives the following configuration:
Priveledged and User mode access to CP10 and CP11.

Primary Region Remap Register c10, c2, 0:
0xff0a81a8
This gives the following configuration:
NOS7-0: 0xFF (Should be write ignored)
Mapping of S = 1 attribute for Normal Memory: 1 = Region is shareable
Mapping of S = 0 attribute for Normal Memory: 0 = Region is not shareable
Mapping of S = 1 attribute for Device Memory: 1 = Region is shareable
Mapping of S = 0 attribute for Device Memory: 0 = Region is not shareable
Primary TEX mapping for memory attributes (TRn):
TR0: 0x00 = Strongly Ordered
TR1: 0x10 = Normal Memory
TR2: 0x10 = Normal Memory
TR3: 0x10 = Normal Memory
TR4: 0x01 = Device Memory
TR5: 0x10 = Normal Memory
TR6: 0x00 = Strongly Ordered
TR7: 0x10 = Normal Memory

Normal Memory Remap Register c10, c2, 1:
0x40e040e0
This gives the following configuration:
Outer Cacheable property mapping for memory attributes n (ORn):
OR0: 0x00 = Region is Non-cacheable
OR1: 0x00 = Region is Non-cacheable
OR2: 0x10 = Region is WriteThrough, Non-WriteAllocate
OR3: 0x11 = Region is Write-Back, Non-WriteAllocate
OR4: 0x00 = Region is Non-cacheable
OR5: 0x00 = Region is Non-cacheable
OR6: 0x00 = Region is Non-cacheable
OR7: 0x01 = Region is Write-Back, WriteAllocate
Inner Cacheable property mapping for memory attributes n (IRn):
IR0: 0x00 = Region is Non-cacheable
IR1: 0x00 = Region is Non-cacheable
IR2: 0x10 = Region is WriteThrough, Non-WriteAllocate
IR3: 0x11 = Region is Write-Back, Non-WriteAllocate
IR4: 0x00 = Region is Non-cacheable
IR5: 0x00 = Region is Non-cacheable
IR6: 0x00 = Region is Non-cacheable
IR7: 0x01 = Region is Write-Back, WriteAllocate

Control Register c1, c0, 0:
0x10c53c7d
This gives the following configuration:
MMU Enable: 1
Enable Strict Alignment: 0
Data Caching Enabled: 1
Enable Program Flow prediction: 1
Instruction Caching Enabled: 1
Exception Vector Location: 1 = High Exception Vectors (0xFFFF_0000-0xFFFF_001C)
E-bit setting: 0
Non-Maskable Fast Interrupt enable: 0
Tex remap functionality: 1 = TEX remap enabled
Access Flag Enable: 0
Thumb Exception Enable: 0



Is there something I am missing or am I configuring something incorrectly?

Thanks,Robert VanVossen
  • Note: This was originally posted on 31st October 2012 at http://forums.arm.com

    Thank You! I have now fixed my problem.

    The page table entries and the ttbr can be marked as shareable, but the PRRR bits need to all be marked as not shareable.
    NS1: 0
    NS0: 0
    DS1: 0
    DS0: 0

    It seems to have been a problem with regions.
  • Note: This was originally posted on 31st October 2012 at http://forums.arm.com


    Thank You! I have now fixed my problem.

    The page table entries and the ttbr can be marked as shareable, but the PRRR bits need to all be marked as not shareable.
    NS1: 0
    NS0: 0
    DS1: 0
    DS0: 0

    It seems to have been a problem with regions.


    I spoke too soon. The bit DS1 still needs to be set to 1. This allows access to the hardware registers. Changing NS1 to 0 was all that was needed to fix my issue.
  • Arm Employee Badge
    Note: This was originally posted on 31st October 2012 at http://forums.arm.com

    I think the problem is that you've marked the memory as shared (Shareable: 1).

    The shareable/shared attribute is about which other masters the address is shared with.  Non-shared means your not sharing it with anyone else, shared means you are.  For shared locations the processor has to use exclusive monitoring (a  Global Monitor) in the memory system.  So that accesses by the processor and the other masters sharing the location are all visible.  For non-shared, the processor does the monitoring internally.

    Thing is.... not all memory systems will provide a Global Monitor.  Or, if they do - it may not cover all addresses.  I don't have a Beagle xM (but.. it is almost Christmas...)  but my guess is that this is what is causing you problems.