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ARM PMU - Event 0x56 - No instructions for issue (A8)

Prabindh Sundareson
Note: This was originally posted on 30th October 2012 at http://forums.arm.com

[font=Arial][size=2]I am using peemuperf (https://github.com/prabindh/peemuperf/blob/master/README.md) to get various cache profile results from ARM PMU, and some specific EMIF counters available in TI processors. I am currently looking at one of the A8 processors. In ARM Performance monitoring unit, the SEL field (event ID) of [/size][/font]EVTSEL register can be used to select the event ID.[size=2]  In this, 0x56 is defined to indicate "[/size]0x56 ==> Increment for every cycle that no instructions are available for issue[size=2]". [/size]

  [font=Arial][size=2] [/size][/font]

  [font=Arial][size=2]With the goal of finding cycles lost because CPU is waiting for I-cache miss and refill to be available, when 0x56 is used, I see some correlation, but with below issues:[/size][/font]

  [font=Arial][size=2] [/size][/font]

  [size=2]-          [/size][font=Arial][size=2]At no-load conditions (no UI or other application, CPU load being negligible), this counter gives cycles equal to that of CPU clock speed. In a 720 MHz processor, I see 720M cycles. This does not match with the description. What is the explanation ?[/size][/font]

  [font=Arial][size=2] [/size][/font]

  [size=2]-          [/size][font=Arial][size=2]At high loads, there is a more meaningful number coming out of the counter, but still it appears to be high, that indicates to me that this cycle count is not just that of CPU waiting for I-cache refills.[/size][/font]

  [font=Arial][size=2] [/size][/font]

  [font=Arial][size=2]Is there a better explanation/ validated results available ?[/size][/font]

  [font=Arial][size=2] [/size][/font]

Parents
  • Arm Employee Badge
    Note: This was originally posted on 30th October 2012 at http://forums.arm.com

    [color=#222222][font=Arial][size=2]>This does not match with the description.[/size][/font][/color]
    [color=#222222][font=Arial][size=2]
    [/size][/font][/color]
    [color=#222222][font=Arial][size=2]It seems like it very closely matches the description. For every cycle no instructions are issued to the pipeline the counter is incremented. Thew counter makes no assumptions about what causes a lack of issue - so wfi/wfe/cache miss are all valid reasons for the counter to increment.[/size][/font][/color]
    [color=#222222][font=Arial][size=2]
    [/size][/font][/color]
    [color=#222222][font=Arial][size=2]Iso[/size][/font][/color]
Reply
  • Arm Employee Badge
    Note: This was originally posted on 30th October 2012 at http://forums.arm.com

    [color=#222222][font=Arial][size=2]>This does not match with the description.[/size][/font][/color]
    [color=#222222][font=Arial][size=2]
    [/size][/font][/color]
    [color=#222222][font=Arial][size=2]It seems like it very closely matches the description. For every cycle no instructions are issued to the pipeline the counter is incremented. Thew counter makes no assumptions about what causes a lack of issue - so wfi/wfe/cache miss are all valid reasons for the counter to increment.[/size][/font][/color]
    [color=#222222][font=Arial][size=2]
    [/size][/font][/color]
    [color=#222222][font=Arial][size=2]Iso[/size][/font][/color]
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