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exclusive access in Origen board

Lee Wang
Note: This was originally posted on 16th September 2012 at http://forums.arm.com

hi, i'm making a little distributive calculation project  on Origen board almost totally based on CortexA2x2_RTSM example downloaded from this site.

everything goes fine, until lockMutex realization. strex instruction always returns 1, even though, it writes value to memory. seems that monitors didn't tag physical address as exclusive access after ldrex instruction, but mmu was turned on fine and memory range that contains mutex-values was "normal sharable" (this part was taken totally from CortexA2x2_RTSM).

please. help me to figure out what the problem is.




  • Note: This was originally posted on 18th September 2012 at http://forums.arm.com


    Best guess would be that the core is trying to use the Global Monitor, and that there isn't one.  So the "exclusive" bus accesses always return failure (technically OKAY instead of EXOKAY). 

    So the question would be why is the core trying to use the Global Monitor....  Some things to check:
    * Is the L1 data cache turned on?  It needs to be.
    * Are the ACTLR.SMP and ACTLR.FW  bits set?  And is the SCU enabled? 
    * You said the region is marked as normal+shareable, is it also write-baclk/write-allocate


    thanks a lot. i just forgot to enable cache. seems it's work fine already :)
  • Arm Employee Badge
    Note: This was originally posted on 17th September 2012 at http://forums.arm.com

    Best guess would be that the core is trying to use the Global Monitor, and that there isn't one.  So the "exclusive" bus accesses always return failure (technically OKAY instead of EXOKAY). 

    So the question would be why is the core trying to use the Global Monitor....  Some things to check:
    * Is the L1 data cache turned on?  It needs to be.
    * Are the ACTLR.SMP and ACTLR.FW  bits set?  And is the SCU enabled? 
    * You said the region is marked as normal+shareable, is it also write-baclk/write-allocate