• Locked Locked
  • Replies 5 replies
  • Subscribers 118 subscribers
  • Views 4445 views
  • Users 0 members are here
Options
Related
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Memory alignment while using LDR instruction in cortex A9

ANGEL MARY NATHAN
Note: This was originally posted on 3rd August 2012 at http://forums.arm.com

Hi,

I am facing some problem while trying to load a 32 bit value into a register by using LDR R0 [R1] where R1 is a pointer to a memory location having some value.
when i use the LDR instruction 3bytes are fetched from the location pointed by R1 and the 4th byte is 1byte before the loacation pointed by R1.
I am working on ARM Cortex A9 simulator.
Is it anything related to memory alignment?
How do i solve this?

Thanks in advance
Angel
  • Note: This was originally posted on 6th August 2012 at http://forums.arm.com

    HI ttfn,

    The value of R1(pointer) is 0x403023cd.
    Im using CCS V5, In the properties i have chosen cortex R4.

    The memory looks like

    address     0x403023cc   0x403023cd             0x403023ce               0x403023cf                 0x403023d0               

    value                  0x4E                   0X4D                      0X4C                         0X4B                          0X48    

    R1 is pointing to 0x403023cd
    when I try loading LDR R0,[R1], the value i get in R1 IS 4E4B4C4D.
    How do i solve this?
  • Note: This was originally posted on 7th August 2012 at http://forums.arm.com

    Hai isogen74,

    Thanks for the reply.

    So do you mean to say the simulator is not installed properly.

    Is there any changes in the settings that i could make to make it treat the unaligned memory properly.
  • Arm Employee Badge
    Note: This was originally posted on 3rd August 2012 at http://forums.arm.com

    What is the value of R1 (specifically the bottom bits)?  And which simulator are you using?

    What you describe sounds like what pre-v6 processors did for unaligned accesses.
  • Arm Employee Badge
    Note: This was originally posted on 6th August 2012 at http://forums.arm.com

    Hmm - it looks like the simulator is not correctly handling unaligned loads. Depending on setup I would either expect:

       * An alignment fault
       * An unaligned access (0x4D, 0x4C, 0x4B, 0x48)

    I'd suggest talking to the vendor of the simulator.
  • Arm Employee Badge
    Note: This was originally posted on 7th August 2012 at http://forums.arm.com

    Based on the information you've given it looks like a bug in the simulator. The memory access pattern it is performing (accessing memory below the current address in a different word) is not something an ARM core would ever do.