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PL390 GIC Interrupt Grouping

Stefan Kalkowski
  • Note: This was originally posted on 26th July 2012 at http://forums.arm.com

    Hi,

    thank you for your fast response!


    Do you really mean the PL390, or the integrated IC in the MPCore?  Not that it matters too much at this point.


    Yes, I meant the integrated IC. Thought of it to be PL390, but I can't  find the TRM section that led to this impression.


    I think this is a GICv1 vs GICv2 spec thing which I've hit in the past.  In GICv2 the secure copy of the GICD_CTLR has enable bits for group 0 and 1.  In GICv1 the secure GICD_CTRL is _only_ required to have the group 0 enable bit, it is IMPLEMENTATION DEFINED whether bit 1 is the group 1 enable.  :-(  The PL390/GIC-390 (which is GICv1) does not implement this bit.


    Just to clarify this: I probably cannot use the EnableGrp1 bit in this implementation, but only have to enable EnableGrp0 in the normal world. After that interrupt grouping should work for this GICv1 IC (at least it has security extensions enabled, I've checked that in the interrupt-type-register) too, right? In that case the problem lies somewhere else in my implementation, but nevertheless it would be pleasant to hear whether interrupt grouping works in general with this interrupt controller ;-).

    Regards
  • Arm Employee Badge
    Note: This was originally posted on 25th July 2012 at http://forums.arm.com

    Do you really mean the PL390, or the integrated IC in the MPCore?  Not that it matters too much at this point.

    I think this is a GICv1 vs GICv2 spec thing which I've hit in the past.  In GICv2 the secure copy of the GICD_CTLR has enable bits for group 0 and 1.  In GICv1 the secure GICD_CTRL is _only_ required to have the group 0 enable bit, it is IMPLEMENTATION DEFINED whether bit 1 is the group 1 enable.  :-(  The PL390/GIC-390 (which is GICv1) does not implement this bit.