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CA9MP - Join and Leave coherency

Shlomi(OBSOLETE) Shamam over 12 years ago

Note: This was originally posted on 23rd July 2012 at http://forums.arm.com

Hi,

I have some thoughts regarding joining and disengaging cores to the coherency:
In the bootstrap, the case is very easy, the primary core enables the SCU and the secondary cores join to coherency by setting ACTLR.SMP after the L1 caches have been invalidated.
But, assume that one of the CA9 cores wish to leave the coherency.
What actions should be taken for doing it propely?
What happens to the data that was stored in that cache?

Thanks,
Shlomi

Shlomi(OBSOLETE) Shamam over 12 years ago

Note: This was originally posted on 24th July 2012 at http://forums.arm.com

Hi,
Thanks for replying.

I'm wondering, what happens to the data in the D cache that just has been disabled. i.e. let's say that core X decides to leave the SMP and the data in its cache is dirty and used by core Y for read. Will core Y get a stale data from L2/L3 memory? Perhaps, cache clean and invalidation should be broadcasted?

Thanks,
Shlomi
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Martin Weidmann over 12 years ago

Note: This was originally posted on 24th July 2012 at http://forums.arm.com

* Disable the L1 D cache (by clearing SCTLR.C bit)
* Clean and invalidate L1 D cache
* Leave coherency management (clear ACTLR.SMP)
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