Hi,
The Cortex-A53 core supports either ACE or CHI as its master interface. Assuming I don't need any of the coherent features introduced in the ACE specification, is there any functional problem if Cortex-A53 ACE interface is connected to an AXI-4 interconnect assuming I tie off all the ready signals introduced in the ACE specification to 1.
Thanks.
If you look in the A53 TRM, you'll see that there's an AXI3 compatibility mode, which will allow it to connect to an AXI4 interconnect - https://developer.arm.com/docs/ddi0500/latest/level-2-memory-system/ace-master-interface/axi3-compatibility-mode. It's probably easier to view as a PDF.
You'll want to tie all the ACE specific inputs low, instead of high though.