Hi,
The Cortex-A53 core supports either ACE or CHI as its master interface. Assuming I don't need any of the coherent features introduced in the ACE specification, is there any functional problem if Cortex-A53 ACE interface is connected to an AXI-4 interconnect assuming I tie off all the ready signals introduced in the ACE specification to 1.
Thanks.
Hi Ed Leung
I've moved your post to Processors where I think you're more likely to get an answer.