Hello Guys,
in my system ( multi core cortex- a7 ), I do not want to be in SMP mode that means it is AMP mode and i need to clear the ACTLR.SMP bit to be in AMP mode but the strange thing which i found though cortex-a7 MPCore TRM is that , those L1 data cache and unified caches will be disabled if SMP bit is cleared. that means i can not use L1 data cache and unified cache in AMP mode.
i don't really know if my above understanding is clear or not but different tests which i performed by enabling and disabling SMP bit approves my understanding.
any one out there who can clear this point and help me out.
would like to thanks in advance for the answers..!!
Regards,
Ashwin.
Hello Bastian,
thanks for your reply.
yes i have setup MMU and also enabled M,C and I bits in SCTLR
i agree with you that disabling "SMP" means, there is no cache coherence between the L1 caches of cores. but the there is a statement in cortex-a7 MPcore TRM which is causing me trouble. statement is there in table "Table 4-52 SCTLR bit assignments" below description of "C" bit which states "The caches are disabled when ACTLR.SMP is set to 0 regardless of the value of the cache enable bit" that means in AMP mode( SMP bit cleared ) caches are disabled. any justification for the above statement mentioned in TRM. would appreciate if you can provide.
Wow, now this is strange. And only a small note.Anyway, why can't you use SMP mode? The only "impact" I see is the cache coherency protocol.
Yes. that can be done with some condition apply. but that is the story for another day currently i am worried about the statement provided ( mentioned in my previous reply ) TRM. and seek clarification for the same.
Yes, it is a bit thrilling that the caches are disabled totally. I cannot remember seeing this in other cores.Hope some ARM employer reads this thread and sheds some light on it.
Hoping the same. thanks for your time Bastian..!!