Since ARM caches are physically indexed is there any way to flush based on the PA? I know I can get the set, but what about the way? If I am flushing from L1 would I have to flush all ways in L1 and then L2 assuming there is no L3 to get to system memory?
Is there an example of this written somewhere? All examples I have seen use VA.
Thanks!
If we take other Processing Elements but ARM cores than yes, there could be loads of them: except DMA, there is DSP, another Cortex, eg. M integrated into SoC, FPGA outside of the SOC, etc.. Some may have coherent caches such as ARM and/or DSP if configured to being able to send and receive snoops and other won't as being able only to send snoops.
But unless implemented these other Elements cannot run (manual) Cache Maintenance Operations though they may participate in the coherency managed in HW.
On top, though I'm by no means an expert in this, only know of, the system may have the System MMU. Then even the DMA shouldn't need to know the PA2VA mapping as operates only on VA.