Hello experts,
In my project I need to write some bare metal code in order to boot my software (A VxWorks image), and would like to make the absolute minimum configurations before loading the VxWorks image, which then does the major part of the configurations.
I'm running on a Cortex A53, specifically on an LS1043ARDB board.
After POR I'm in S.EL3 of course, in which I configure all the SCTLR VBAR and SCR registers (I also initilze the RAM controller of course). I leave cache disabled as the VxWorks image will afterwards take care of cache settings.
After jumping to the VxWorks code, it will come up just fine, do the settings and bring itself to NS.EL1, then at some point it makes an smc #0 call in order to use some secure world functionality. Now instead of being vectored to EL3 offset 0x400 ("sync from lower level with current level sp") as expected, it stays in NS.EL1. and is vectored to offset 0 in the vector table which is the "sync with sp0" entry.
If I use U-Boot for boot loading my image all is fine and dandy, so appearantly U-Boot is doing something I don't.
Can anyone please help and let me know if I'm missing any configuration? Is there anything that needs to be configured in order for the CPU to be able to take an exception from NS.EL1 to EL3 via an smc call?
Thanks in advance.
All you wrote look fine to me. As the devil may be in a detail I don't think I can help without inspecting your code.
I can also suggest that you look and compare your boot code against the Secure Monitor/ATF in the "cold boot" path.
I will be in the office only next week so I will be able to send a code snippet.
Where can I find the secure monitor/ATF source code?
github.com/.../arm-trusted-firmware.git
Thank you!