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M4 Assembly - Set Enable also enables the Clear Enable Interrupt Register

marcusob

Hi,

I have some assembly for Cortex M4 (Arm 7M Thumb), I want to enable an interrupt that is connected to a push button on an STM32 F407. It works, but for some reason when I enable the set enable register, the clear enable register also gets set ? Is this normal ?

NVIC_BASE           EQU     0xE000E100
NVIC_ISER0          EQU     NVIC_BASE
SETENA6             EQU     1 << EXTI0_IRQn

EnableButtonINT PROC
    ;Enables the interrupt for the blue pushbutton
    LDR     r0, =NVIC_ISER0         ;set enable interrupt from EXTI0_IRQn channel
    LDR     r1, =SETENA6
    STR     r1, [r0]
    BX      LR
    ENDP   

So the code above results in 0x40 on set enable AND clear enable registers !

The reason I ask is that I seem to be getting two interrupts all the time. I've put a debounce on so my flow is

1. Enable interrupts

2. On button interrupt - toggle LED, disable button interrupt (for debounce), use the systick timer to get another interrupt in 200ms

3. On systick interrupt (200 ms after button press), re-enable button interrupt again ie debounce finished

So I'm disabling the button interrupt to prevent repeated button interrupts when user is really only pressing ovce (typical debounce). But I get an interrupt for button on, then when the re-enable occurs I get another one straight away (I've cleared enabled and pending).