Hi,
This is in the context of the Cortex-M3 and PrimeCell uDMAC as implemented in the Texas Instruments CC2640R2F Bluetooth controller (I have gone through the TI support forums for this question but it seems that this is fully within the ARM IP domain).
From reading the ARM documents, I see that the MCU core access to memory and uDMAC access to memory and peripherals all occur on the same (system) bus and that the MCU core has priority over the uDMAC...
Is there any provision in this architecture for the MCU core to yield to the uDMAC every, say, 16 bus cycles? I cannot see any mention of such in the documentation so I am assuming that there is not. Can anyone kindly confirm?
Regards,
ac
Colin,
Many thanks for your prompt and detailed response. Let me go back to TI and dig further.