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How to start Firmware separated in I-RAM and D-RAM within Cortex-M3 design kit?

Hello?

I'm trying to implement the Firmware with the Cortex-M3 SoC which is separately designed I-RAM and D-RAM  in Keil MDK.

As you can see the above example system, AHB Interconnect have 3 slaves S0, S1 and S2. and S0 and S1 are connected with separated SRAM, especially, If it can be, I'd like to make the firmware to allocate each address region separately.

For example, the system consisted as the below.

S0 address map  0x00000000 ~ 0x0000FFFF

S1 address map  0x00010000 ~ 0x0001FFFF

It means that I'd like to run the I-Code part of firmware into I-Ram and the D-Code part of firmware into D-Ram.

In this case, My question is

1.How to start Firmware separated in I-RAM and D-RAM within Cortex-M3 design kit by using Keil MDK?

2.How to assign or calculate the S0 and S1 addresses region at the first time of initial architecture designing?

3.How to determine the I-RAM and D-RAM size ?