Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before starting copy by DMA, I clean data cache by MVA to point of coherency and I use DSB to stop CPU to be sure, that data are in memory. Then I start copy by SDMA.
My problem is, that one per thousands times, SDMA copies old data. CPU doesn't stall to complete memory operations or it changes the order of executin software. How can I solve the problem?
Have you seen the barriers example in the Arm ARM? In the ARMv7-A/R Arm ARM, they are in chapter D7.5.1
I haven't proper document because I haven't this chapter. Where can I find your document?
I find this chapter.