Hi,
I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.
My question is how should I interpret the shareability domain: inner, outer controlled through TCR register and the page descriptor. Would be that inner shareable is within the Cluster and only within it the Coherency is maintained for the Memory region marked Cacheable WB-WA for Innter and Outer?
Or is my understanding wrong in the context of "Snoop and Maintenance Requests" chapter of "ARM Cortex-A53 MPCore Processor TRM". It says there that broadcastinner asserted enforces broadcastouter asserted so that would suggest that setting the inner shareability makes snoop and maintenance requests boradcast to the Observers in both Inner and Outer Domains.
Please help!
Thanks,
Marek
For 5) yes. In the example system described in Example B2-1, the different clusters would typically, but not mandatory, be running different OS's. The document is only referring to expected use case but the architecture does not explicitly forbid running multiple OS's running in the same inner shareable domain.
For 6) Even If you mark your memory as outer shareable, there is no guarantee that coherence "Will" get maintained. The SOC hardware may not even have(or recognize, or may simply force that OSH = ISH) an outer shareable domain. It is possible that the SOC is designed in such a way that coherency between the clusters is expected to be maintained manually. You may want to mark your memory as outer shareable and experiment to see if coherency is maintained but the safest approach to designing software for the SOC would be to know exactly how the SOC is designed to avoid ending up with hard to debug coherency issues. In your case, as stated earlier, it is possible that L1/L2 are inner caches and L3;s are outer caches but are all part of the inner shareable domain in which case you can just mark all your memory as innershareable and not have to worry about coherency between clusters.
Great. Thank you Raghu. This is invaluable information. I have requested the HW design team to let me know these.