Hi all,
A Question about the A8 processor.
If I enable the L1 and L2 caches, I see a performance boost even if the MMU is disabled. I was under the impression that the MMU is required to be enabled to use the Cache. I also do not see any errors or mismatches. My project works the same way whether cache is disabled or enabled(better performance in the second case), leading me to believe that there are no problems with using the cache without enabling the MMU. Is this the expected behavior?
Additionally, I am also defining the page directory to mark the uncacheable memory. This also seems to work when I do not enable the MMU. Can I ignore the MMU and use the cache safely?
I read this post but I am still not clear on what to expect from a software point of view.
For further context, I am using the BBB device for a a project which requires good performance, when I stumbled on this. This does not require virtual memory. It needs uncacheable memory for some device drivers which use DMA. Every other piece of memory can be cached and all processes share the same address space.
Cheers!
There is a default cache behavior which applies to _all_ memory as long as the MMU is disabled.
See chapter "B3.2.1 VMSA behavior when a stage 1 MMU is disabled" in the Cortex-A TRM (ARM DDI 0406C.c):
-data: "The stage 1 translation assigns the Strongly-Ordered memory type.Note This means the access is Non-cacheable. Unexpected data cache hit behavior is IMPLEMENTATION DEFINED."
- instruction: "The stage 1 translation assigns the Cacheable, Inner Write-Through no Write-Allocate, Outer Write-Through no Write-Allocate attribute."