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Hi, accorting to the reference manual of cortex A7 https://static.docs.arm.com/ddi0464/f/DDI0464.pdf
pagina 243, what event number i neet to select to count all the DRAM access (read / write)?
I agree to your point. Can you explain me then what is the significance of Bus Access Write and Bus access Read in A55 and A76? Why there are two seperate events if they are counting the same?
Why should these two be the same? One is read the other write.